Edge termination for super-junction MOSFETs

• US 9,882,044 B2
• Filed: 08/19/2015
• Issued: 01/30/2018
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US14/830,277
• Publication Number:
  US 20160056281A1
• Time in Patent Office: 895 Days
• Field of Search: 257330, 257329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core super-junction region including a plurality of parallel core plates coupled to a source terminal of the super-junction MOSFET. The super-junction MOSFET also includes a termination region surrounding the core super-junction region comprising a plurality of separated floating termination segments configured to force breakdown into the core super-junction region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.

Claims

1. A vertical trench MOSFET comprising:

a substrate of first conductivity;

a plurality of gate trenches descending beneath a surface of said substrate,

wherein each gate trench comprises one or more gates of said MOSFET;

source and body regions of said MOSFET in a mesa between said gate trenches;

a drift region below said gate trenches and below said source and body regions, said drift region comprising;

a plurality of core plates of a second conductivity alternating with regions of said first conductivity, wherein said core plates are coupled to said source regions of said MOSFET;

a termination region surrounding said drift region at about the same depth as said drift region, said termination region comprising;

a plurality of separated floating termination segments of said second conductivity formed in said substrate, separated from one another by regions of said first conductivity,

wherein there are no gates of said MOSFET above said termination region, and

wherein each of said termination segments has a length dimension not greater than a length dimension of said core plates.

2. The MOSFET of claim 1 wherein said termination segments are wider than said core plates.

3. The MOSFET of claim 1 wherein a charge of one said termination segments is about equal to the magnitude of a charge in a region separating said termination segment from an adjacent termination segment.

4. The MOSFET of claim 1 wherein a charge of said first conductivity is greater than a charge of said second conductivity in said termination region.

5. The MOSFET of claim 1 wherein said termination segments have rounded corners of radius much less than their diagonal dimension.

6. The MOSFET of claim 1 wherein termination segments at a corner of said termination region are reduced in extent to approximate a rounded corner of said termination region.