Body tie optimization for stacked transistor amplifier

• US 9,882,531 B1
• Filed: 09/16/2016
• Issued: 01/30/2018
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Willard, Simon Edward, Olson, Chris, Ranta, Tero Tapio
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US15/268,257
• Time in Patent Office: 501 Days
• Field of Search: 330277, 330311
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/297 the loading circuit of an amplifying stage comprising a capacitor
• CPC Class Codes: H03F 2200/42 the input to the amplifier being made by capacitive coupling means
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/48 the output of the amplifier being coupled out by a capacitor
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence

Abstract

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Claims

1. A circuital arrangement comprising:

a transistor stack configured to operate as a radio frequency (RF) amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor for receiving an input RF signal to the amplifier, and an output transistor for outputting an output RF signal that is an amplified version of the input RF signal;

the transistor stack configured to operate between a supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor;

one or more gate capacitors each connected between a gate of a transistor of the plurality of stacked transistors, except the input transistor, and a reference ground, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor,

wherein at least one transistor of the plurality of stacked transistors is a four-terminal transistor, and remaining transistors of the plurality of transistors are three-terminal transistors.

2. The circuital arrangement according to claim 1, wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of the output transistor across the plurality of stacked transistors.

3. The circuital arrangement according to claim 1, wherein the at least one transistor of the plurality of stacked transistors is the input transistor.

4. The circuital arrangement according to claim 1, wherein the at least one transistor of the plurality of stacked transistors is the output transistor.

5. The circuital arrangement according to claim 1, wherein the at least one transistor of the plurality of stacked transistors is the input transistor and the output transistor.

6. The circuital arrangement according to claim 1, wherein the at least one transistor of the plurality of stacked transistors is a transistor except the input transistor and the output transistor.

7. The circuital arrangement according to claim 1, wherein the at least one transistor of the plurality of stacked transistors is the plurality of stacked transistors.

8. The circuital arrangement according to claim 1, wherein the plurality of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

9. The circuital arrangement according to claim 8, wherein the plurality of transistors are fabricated using one of:

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

10. The circuital arrangement according to claim 8, wherein the plurality of transistors are one of:

a) N-type transistors, and b) P-type transistors.

11. The circuital arrangement according to claim 1, wherein the supply voltage is a varying supply voltage.

12. The circuital arrangement according to any one of claims 1 and 2-11, wherein a body of the at least one transistor of the plurality of transistors is coupled to a source of said transistor through an impedance of a corresponding body tie.

13. The circuital arrangement according to any one of claims 1 and 2-11, wherein a body of the at least one transistor of the plurality of transistors is coupled to a fixed reference potential through an impedance of a corresponding body tie.

14. A method for manufacturing a radio frequency (RF) amplifier, the method comprising:

providing a substrate comprising one of;

a) silicon-on-insulator substrate, and b) a silicon-on-sapphire substrate; and

manufacturing, on the substrate, a transistor stack configured to operate as a radio frequency (RF) amplifier, the transistor stack comprising;

a plurality of series connected transistors comprising at least one four-terminal transistor and remaining three-terminal transistors; and

one or more gate capacitors each connected between a gate of a transistor of the plurality of series connected transistors, except an input transistor, and a reference ground, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor.

15. The method according to claim 14, wherein the at least one four-terminal transistor is an input transistor of the amplifier.

16. The method according to claim 14, wherein the at least one four-terminal transistor is an output transistor of the amplifier.

17. The method according to claim 14, wherein the at least one four-terminal transistor is an input transistor of the amplifier and an output transistor of the amplifier.

18. The method according to claim 14, wherein the at least one four-terminal transistor is all the transistors of the plurality of series connected transistors.

19. The method according to claim 14, wherein a body of the at least one four-terminal transistor is coupled to a source of said transistor through an impedance of a corresponding body tie.

20. A method for improving a performance of a radio frequency (RF) amplifier, the method comprising:

providing a plurality of floating devices;

configuring the plurality of floating devices as a cascoded stack comprising an input floating device and cascode floating devices;

coupling gate capacitors between gates of the cascode floating devices and a reference ground, the gate capacitors configured to allow gate voltages at said gates to vary along with radio frequency (RF) voltages at drains of the cascode floating devices;

based on the configuring and the coupling, obtaining an RF amplifier having a characteristic performance;

replacing, in the cascoded stack, at least one floating device of the plurality of floating devices with a body tied device;

based on the replacing, obtaining an RF amplifier having an improved characteristic performance; and

fabricating the RF amplifier with improved characteristic performance on one of;

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

21. The method according to claim 20, wherein the replacing comprises replacing an input transistor of the cascoded stack so as to improve a power added efficiency (PAE) of the RF amplifier.

22. The method according to claim 20, wherein the replacing comprises replacing an input transistor of the cascoded stack so as to reduce a leakage current of the RF amplifier.

23. The method according to claim 20, wherein the replacing comprises replacing an output transistor of the cascoded stack so as to improve a withstand voltage capability of the output transistor.

24. The method according to claim 20, wherein the replacing comprises replacing all of the plurality of floating devices so as to improve a transient response of the RF amplifier.

25. A method for reducing a stack height of an RF amplifier, the method comprising:

providing a level of a voltage across a stack;

providing a withstand voltage capability of a three-terminal device;

based on the level of the voltage and the withstand voltage capability, determining a height of the stack based on a required number of series connected three-terminal devices in the stack;

replacing two or more of the series connected three-terminal devices with a reduced number of one or more four-terminal devices;

based on the replacing, reducing the height of the stack; and

fabricating the RF amplifier with reduced stack height on one of;

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).