Test apparatus for generating reference scan chain test data and test system

• US 9,885,752 B2
• Filed: 08/12/2010
• Issued: 02/06/2018
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Seuring, Markus, Braun, Michael
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/816,725
• Publication Number:
  US 20160356847A1
• Time in Patent Office: 2,735 Days
• Field of Search: 714727, 714724, 714730, 714734
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318561 Identification of the subpart
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

Claims

1. A test system comprising:

a test pattern generator configured to;

receive an input scan chain;

generate a modified input scan chain by replacing a first predefined number of start bits of the input scan chain with a predefined start bit sequence; and

provide the modified input scan chain to a device under test (DUT); and

an output data modifier and configured to;

receive an output scan chain that is generated by the DUT in response to the modified input scan chain;

generate a modified output scan chain by replacing a second predefined number of end bits of the output scan chain with a predefined end bit sequence; and

obtain first reference scan chain test data based on the modified output scan chain.

2. The testing system according to claim 1, wherein the first predefined number of start bits and the second predefined number of end bits are determined based on a supposed failure position within a scan chain circuit, and wherein the first reference scan chain test data comprises the modified output scan chain, a frequency of occurring logic 1s or logic 0s of each bit position of the output scan chain, and/or a last toggled bit position indicating a position of the last bit within the output scan chain.

3. The test system according to claim 1, wherein the first predefined number plus the second predefined number is equal to a number of bits of the input scan chain, and equal to a number of bits of the output scan chain.

4. The test system according to claim 1, wherein the predefined start bit sequence and the predefined end bit sequence are determined based on a supposed failure type that is associated with the first reference scan chain test data.

5. The test system according claim 1, wherein the predefined start bit sequence and the predefined end bit sequence comprises only logic 0s or only logic 1s.

6. The test system according to claim 1 wherein the output scan chain is generated by a faultless scan chain of the DUT in response to the modified input scan chain.

7. The test system according to claim 1, wherein the test pattern generator is further configured to:

provide the input scan chain to a faulty BUT that comprises a faulty scan chain circuit; and

wherein a faulty output scan chain is generated by the faulty scan chain in response to the input scan chain.

8. The test system according to claim 7 further comprising an evaluation unit configured to:

compare information derived from the faulty output scan chain with the first reference scan chain test data; and

determine a failure position and a failure type in the faulty scan chain circuit.

9. The test system according to claim 1,

wherein the test pattern generator is further configured to:

receive a plurality of different input scan chains, replace the first predefined number of start bits with the predefined start bit sequence in each of the plurality of different input scan chains, and generate a plurality of modified input scan chains; and

wherein the output data modifier is further configured to;

receive a plurality of output scan chains generated in response to the plurality of modified input scan chains;

replace the second predefined number of end bits with the predefined end bit sequence in each of the plurality of output scan chains;

generate a plurality of modified output scan chains; and

obtain second reference scan chain test data based on the plurality of modified output scan chains.

10. The test system according to claim 9 further comprising a frequency determiner configured to determine a frequency of occurring logic is or logic 0s for each bit position of the plurality of output scan chains based on the plurality of modified output scan chains, wherein frequency of the occurring logic 1 s and logic 0s are incorporated in the second reference scan chain test data.

11. The test system according to claim 9 further comprising a toggle bit determiner configured to determine a last toggle bit position within an output scan chain of the plurality of output scan chains, and/or to determine a first stuck-at bit position of an output scan chain of the plurality of output scan chains.

12. The test system according to claim 10,

wherein the test pattern generator is further configured to provide a plurality of unmodified input scan chains to a faultless DUT and a faulty DUT;

wherein the frequency determiner is further configured to determine a frequency of occurring logic 1s or logic 0s for each bit position of an unmodified output scan chain for the faultless DUT and for the faulty DUT; and

wherein the evaluation unit is further configured to determine a difference between a frequency of occurring logic 0s or logic 1s determined for the faulty DUT and a frequency of occurring logic 0s or logic 1s determined for the faultless DUT for each position of the unmodified output scan chain, and obtain a failure characteristic accordingly.

13. The test system according to claim 10, wherein the evaluation unit is further configured to determine a difference between a frequency of occurring logic 0s or occurring logic 1s determined from a plurality of modified output scan chains and the frequency of logic 0s or logic 1s determined from the plurality of unmodified output scan chains of the faultless DUT for each bit position of the output scan chain to obtain a reference characteristic for each supposed failure position and failure type, wherein the plurality of modified output scan chains are generated by considering a plurality of different supposed failure positions and different failure types.

14. The test system according to claim 13, wherein the evaluation unit is further configured to compare a failure characteristic with a reference characteristic for each supposed failure position and failure type and determine the failure position and the failure type.

15. The test system according to claim 1,

wherein the test pattern generator is further configured to modify the input scan chain by replacing a plurality of different predefined numbers of start bits with a plurality of different predefined start bit sequences to generate a plurality of modified input scan chains;

and

wherein the output data modifier is further configured to;

receive a plurality of output scan chains generated in response to the plurality of modified input scan chains;

replace a plurality of different predefined numbers of end bits with a plurality of different predefined end bit sequences;

generate a plurality of modified output scan chains; and

accordingly obtain a plurality of reference scan chain test data which are indicative of different supposed failure positions or failure types of a faulty scan chain.

16. The test system according to claim 15 further comprising:

an evaluation unit configured to (1) compare information derived from a faulty output scan chain with each of the plurality of reference scan chain test data; and

/or (2) compare a frequency of occurring logic 1s or logic 0s of a plurality of faulty output scan chains with a frequency of occurring logic 1s or logic 0s of the plurality of reference scan chain test data, wherein the a plurality of faulty output scan chains are generated in response to different input scan chains.

17. The test system according to claim 16, wherein the evaluation unit is further configured to determine a failure candidate list containing possible failure positions, failure types and corresponding confidence levels associated thereof.

18. A circuit for generating reference scan chain test data, the circuit comprising:

a test pattern generator configured to;

receive an input scan chain;

generate a modified scan chain test input bit by replacing a first predefined number of start bits of the input scan chain with a predefined start bit sequence; and

provide the modified input scan chain to a device under test (DUT); and

an output data modifier coupled to the test pattern generator and configured to;

receive an output scan chain that is generated by the DUT in response to the modified input scan chain;

generate a modified output scan chain by replacing a second predefined number of end bits of the output scan chain with a predefined end bit sequence; and

obtain first reference scan chain test data based on the modified output scan chain.

19. A method of determining a failure position and failure type of a scan chain, the method comprising:

receiving a first input scan chain at a test pattern generator;

generating a first modified input scan chain at a test pattern generator by replacing a first predefined number of start bits of the first input scan chain with a predefined start bit sequence;

providing the first modified input scan chain from the test pattern generator to a device under test (DUT), wherein the DUT is configured to generate a first output scan chain in response,

generating a first modified output scan chain at an output data modifier by replacing a second predefined number of end bits of first the output scan chain with a predefined end bit sequence; and

obtaining first reference scan chain test data based on the first modified output scan chain at said output data modifier.

20. The method according to claim 19 further comprising, at said output data modifier;

modifying each of a plurality of different input scan chains by replacing the first predefined number of start bits with the predefined start bit sequence to obtain a plurality of modified different input scan chains;

modifying the first input scan chain by replacing a plurality of different predefined numbers of start bits with a plurality of different predefined start bit sequences to obtain a plurality of modified same scan chain test input bits sequences;

modifying a plurality of output scan chains caused by the plurality of modified, different input scan chains by replacing the second predefined number of end bits by the predefined end bit sequence to obtain first reference scan chain test data for a first supposed failure position and failure type of a scan chain; and

modifying a plurality of scan chain test output bits sequences caused by the plurality of modified, same input scan chains by replacing a plurality of different predefined numbers of end bits corresponding to the plurality of different numbers of start bits with a plurality of different predefined end bit sequences to obtain a plurality of reference scan chain test data that represent a plurality of different supposed failure positions or failure types of the scan chain.

21. The method according to claim 19, comprising, at a frequency determiner, determining a frequency of occurring logic 1 s or logic 0s for each bit position of the first output scan chain based on the plurality of modified same output scan chains, wherein frequencies of occurring logic 1s or logic 0s represent the reference scan chain test data for the first supposed failure position and failure type.