Dynamic current sink for stabilizing low dropout linear regulator (LDO)

• US 9,886,044 B2
• Filed: 02/15/2016
• Issued: 02/06/2018
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Chin-Hsun, Lin, Hao-Yuan, Chou, Chia-Hua
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): SINGH, DAVID ANTHONY
• Application Number:
  US15/043,687
• Publication Number:
  US 20170038783A1
• Time in Patent Office: 722 Days
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G05F 1/462 as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
• CPC Class Codes: G05F 1/467 Sources with noise compensation
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/563 including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/569 for protection
• CPC Class Codes: G05F 1/571 with overvoltage detector
• CPC Class Codes: G05F 1/573 with overcurrent detector
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Claims

1. A dynamic current sink for stabilizing an output voltage at an output node of an LDO (Low Dropout Linear Regulator), comprising:

a first voltage comparator, comparing a first reference voltage with a second control signal from the LDO, so as to generate a first control signal;

a first transistor, wherein the first transistor has a control terminal for receiving the first control signal, a first terminal coupled to a ground voltage, and a second terminal coupled to a first node;

a first current source, supplying a first current to the first node;

a first inverter, wherein the first inverter has an input terminal coupled to the first node, and an output terminal coupled to a second node;

a second current source, supplying a second current to a third node;

an NAND gate, wherein the NAND gate has a first input terminal coupled to the third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node;

a first capacitor, coupled between the fourth node and a fifth node;

a first resistor, coupled between the fifth node and the ground voltage;

a second transistor, wherein the second transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the third node; and

a third transistor, wherein the third transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the output node;

wherein the third transistor is configured to selectively draw a first discharge current from the output node.

2. The dynamic current sink as claimed in claim 1, further comprising:

a second resistor, coupled between the output node and the second terminal of the third transistor.

3. The dynamic current sink as claimed in claim 1, wherein the LDO comprises:

a second voltage comparator, comparing a second reference voltage with a feedback voltage, so as to generate the second control signal;

a fourth transistor, wherein the fourth transistor has a control terminal for receiving the second control signal, a first terminal coupled to a supply voltage, and a second terminal coupled to the output node;

a third resistor, coupled between the output node and a sixth node, wherein the sixth node has the feedback voltage; and

a fourth resistor, coupled between the sixth node and the ground voltage.

4. The dynamic current sink as claimed in claim 3, wherein the fourth transistor is configured to selectively supply a loading current to the output node.

5. The dynamic current sink as claimed in claim 4, wherein if the loading current is changed, an overshoot output voltage or an undershoot output voltage occurs at the output node, and the first discharge current is arranged for stabilizing the output voltage at the output node.

6. The dynamic current sink as claimed in claim 3, wherein the output node is further coupled to a stabilizing capacitor and is arranged for driving an external loading element.

7. The dynamic current sink as claimed in claim 3, wherein the first voltage comparator has a positive input terminal for receiving the first reference voltage, a negative input terminal for receiving the second control signal, and an output terminal for outputting the first control signal, wherein the second voltage comparator has a positive input terminal for receiving the feedback voltage, a negative input terminal for receiving the second reference voltage, and an output terminal for outputting the second control signal, and wherein the fourth transistor is a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor).

8. The dynamic current sink as claimed in claim 1, further comprising:

a second inverter, wherein the second inverter has an input terminal coupled to the fourth node, and an output terminal coupled to a seventh node;

a third current source, supplying a third current to an eighth node;

a fifth transistor, wherein the fifth transistor has a control terminal coupled to the fourth node, a first terminal coupled to a ninth node, and a second terminal coupled to the eighth node;

a second capacitor, coupled between the ninth node and the ground voltage;

a sixth transistor, wherein the sixth transistor has a control terminal coupled to the seventh node, a first terminal coupled to a tenth node, and a second terminal coupled to the ninth node;

a fifth resistor, coupled between the tenth node and the ground voltage; and

a seventh transistor, wherein the seventh transistor has a control terminal coupled to the ninth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the output node;

wherein the seventh transistor is configured to selectively draw a second discharge current from the output node.

9. The dynamic current sink as claimed in claim 8, further comprising:

a sixth resistor, coupled between the output node and the second terminal of the seventh transistor.

10. The dynamic current sink as claimed in claim 8, wherein the first discharge current and the second discharge current have different slopes over time axis.