Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

• US 9,886,193 B2
• Filed: 05/15/2015
• Issued: 02/06/2018
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Berger, Daniel G., Graves-Abe, Troy L., Iyer, Subramanian S., Kirihata, Toshiaki, Kumar, Arvind, Wilcke, Winfried W.
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/713,689
• Publication Number:
  US 20160334991A1
• Time in Patent Office: 998 Days
• Field of Search: 716100
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Claims

1. A processor-memory system comprising:

a wafer including a memory area;

a multitude of specialized processors, each of the specialized processors being embedded within an associated memory domain in the memory area of the wafer, and each of the specialized processors being configured for performing a specified set of operations using said associated memory domain in the memory area of the wafer;

a management processor to control operations of an associated set of the specialized processors.

2. The processor-memory system according to claim 1, wherein each of the specialized processors is embedded within and controls a respective one associated memory domain in the memory area of the wafer.

3. The processor-memory system according to claim 1 wherein:

the wafer comprises a specialized processor wafer; and

each of the specialized processors transmits to the management processor results of the operations using the associated memory domain in the memory area of the wafer.

4. A processor-memory system comprising:

a memory area;

a multitude of specialized processors embedded in the memory area, each of the specialized processors being configured for performing a specified set of operations using an associated memory domain in the memory area; and

a management processor to control operations of an associated set of the specialized processors; and

wherein the management processor includes;

a subordinate general management processor connected to said associated set of the specialized processors for controlling said associated set of the specialized processors, and

a lead general management processor in communication with the subordinate general management processor for transmitting data to and receiving data from the subordinate general management processor.

5. The processor-memory system according to claim 4, further comprising:

a wiring wafer; and

wherein;

the lead general management processor and the subordinate general management processor are connected to the wiring wafer; and

the wiring wafer includes a wiring level connecting the lead general management processor to the subordinate general management processor for transmitting commands and information between the lead general management processor and the subordinate general management processor.

6. A stacked-wafer processor-memory system comprising:

a plurality of specialized processor wafers arranged in a stack, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, and each of the specialized processors performing a specified set of operations using a respective one associated memory domain of the memory area of the each specialized processor wafer;

a plurality of subordinate general management processors, each of the subordinate general management processors connected to and controlling operations of a respective one associated set of the specialized processors; and

a lead general management processor for communicating with the subordinate general management processors and with external input/output connections.

7. The stacked-wafer processor-memory system according to claim 6, wherein:

each of the specialized processor wafers further comprises a wiring level connecting together the specialized processors of the each specialized processor wafer.

8. The stacked-wafer processor-memory system according to claim 6, further comprising:

a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers.

9. The stacked-wafer processor-memory system according to claim 7, further comprising:

a wiring wafer comprising a plurality of wiring levels; and

wherein;

the lead general management processor and the plurality of subordinate general management processors are connected to the wiring levels of the wiring wafer; and

the wiring wafer is mounted on top of the plurality of specialized processor wafers.

10. The stacked-wafer integrated circuit according to claim 6, further comprising an interposer, and wherein:

the plurality of specialized processor wafers are stacked on the interposer; and

the lead general management processor and the subordinate general management processors are mounted on the interposer.

11. A method of fabricating a processor-memory system, comprising:

fabricating one or more specialized processor wafers, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, each of the specialized processors being configured to perform a specified set of operations using an associated memory domain of the memory area of the each specialized processor wafer;

connecting a plurality of subordinate general management processors to the specialized processors, each of the subordinate general management processors being configured to manage an associated set of the specialized processors; and

connecting a lead general management processor to the subordinate general management processors to communicate therewith.

12. The method according to claim 11, wherein:

the fabricating one or more specialized processor wafers includes adding a wiring level to each of the specialized processor wafers to connect together the specialized processors of the each specialized processor wafer.

13. The method according to claim 11, further comprising:

fabricating a wiring wafer, said wiring wafer including wiring levels for the lead general management processor and the subordinate general management processors; and

wherein;

the connecting a plurality of subordinate general management processors to the specialized processors includes connecting the plurality of subordinate general management processors to the wiring levels of the wiring wafer; and

the connecting a lead general management processor to the subordinate general management processors includes connecting the lead general management processor to the wiring levels of the wiring wafer.

14. The method according to claim 13, wherein:

the fabricating one or more specialized processor wavers includes fabricating a plurality of specialized processor wafers; and

the method further comprises;

forming a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers and for communicating with the general management processors;

bonding the plurality of specialized processor wafers together in a stack; and

bonding the wiring wafer onto a top of the stack.

15. The method according to claim 11, wherein the fabricating one or more specialized processor wafers includes:

for each of the specialized processor wafers, forming a wiring pattern connecting together the specialized processors of the each specialized processor wafer, including;

using a common mask to form a wiring layer, and using a mask stepping size the same as a stepping size used for individual specialized processors in the each specialized processor wafer;

using an additional mask for express bus customization; and

connecting together the specialized processors of the each processor wafer using adaptive segmented stitching to allow isolation of defective ones of the specialized processors.

16. A method of fabricating a stacked wafer processor-memory system, the method comprising:

fabricating a plurality of specialized processor wafers, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, each of the specialized processors being configured to perform a specified set of operations using an associated memory domain of the memory area of the each specialized processor wafer;

connecting a plurality of subordinate general management processors to the specialized processors, each of the subordinate general management processors being configured to manage an associated set of the specialized processors;

connecting a lead general management processor to the subordinate general management processors to communicate therewith; and

forming a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers.

17. The method according to claim 16, further comprising:

fabricating a wiring wafer, said wiring waver including wiring levels for the lead general management processor and the subordinate general management processors; and

wherein;

the connecting a plurality of subordinate general management processors to the specialized processors includes connecting the plurality of subordinate general management processors to the wiring levels of the wiring wafer; and

the connecting a lead general management processor to the subordinate general management processors includes connecting the lead general management processor to the wiring levels of the wiring wafer.

18. The method according to claim 17, wherein the connecting the plurality of subordinate general management processors to the wiring levels of the wiring wafer includes bonding the plurality of subordinate general management processors to the wiring wafer using a layer of micro controlled collapse-chip connections.

19. The method according to claim 16, wherein the fabricating a plurality of specialized processor wafers includes adding a wiring level to each of the specialized processor wafers to connect together the specialized processors of the each specialized processor wafer.

20. The method according to claim 16, further comprising:

bonding the plurality of specialized processor wafers together into a stack;

mounting said stack onto an interposer board; and

wherein;

the connecting a lead general management processor to the subordinate general management processors includes mounting the lead general management processor on the interposer board; and

the connecting a plurality of subordinate general management processors to the specialized processors includes mounting the subordinate general management processors on the interposer board.

21. A stacked-wafer processor-memory system comprising:

a plurality of wafers arranged in a stack, including

at least one memory wafer comprising a multitude of memory domains, and

at least one processor wafer comprising a multitude of processors, each of the processors controlling a respective one of the memory domains of the memory wafer;

a multitude of general management processors including

a multitude of subordinate general management processors, each of the subordinate general management processors being connected to a respective one, associated set of the specialized processors for controlling said associated set of the specialized processors, and

a lead general management processor in communication with the subordinate general management processors for transmitting data to and receiving data from the subordinate general management processors; and

a network of through silicon vias for delivering power and ground to the specialized processor wafers and for communicating with the general management processors.

22. The stacked-wafer processor-memory system according to claim 21, wherein:

the at least one memory wafer includes a plurality of memory wafers;

the at least one processor wafer includes a plurality of processor wafers; and

in said stack, the plurality of memory wafer alternate with the plurality of processor wafers.

23. The stacked-wafer processor-memory system according to claim 22, wherein:

each of the plurality of processor wafers includes a wiring level connecting together the processors of said each processor wafer.

24. The cortical structure according to claim 21, further comprising:

a wiring wafer; and

wherein;

the multitude of general management processors are mounted on the wiring wafer.

25. The stacked-wafer processor-memory system according to claim 24, wherein the wiring wafer is mounted on said stack.