Solid state driving including nonvolatile memory, random access memory and memory controller

• US 9,886,379 B2
• Filed: 03/25/2015
• Issued: 02/06/2018
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyunjin, Park, Kitae, Lee, Seonkyoo, Ihm, Jeongdon, Jeon, Youngjin
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): LI, HEWY H
• Application Number:
  US14/668,015
• Publication Number:
  US 20150378885A1
• Time in Patent Office: 1,049 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

Claims

1. A solid state drive comprising:

a nonvolatile memory including a plurality of nonvolatile memory chips and a buffer chip;

a first random access memory (RAM); and

a memory controller configured to control the nonvolatile memory and the first RAM,

wherein the buffer chip is connected between the plurality of nonvolatile memory chips of the nonvolatile memory and the memory controller, and

wherein the memory controller comprises;

an internal bus;

a host interface configured to communicate with an external host device;

a memory interface configured to communicate with the nonvolatile memory;

a buffer control circuit configured to directly exchange data with the host interface without passing through the internal bus, configured to directly exchange the data with the memory interface without passing through the internal bus, and configured to directly exchange the data with the first RAM without passing through the internal bus; and

a processor configured to receive a first command and a first address from the host interface through the internal bus, configured to produce a second command and a second address respectively from the first command and the first address, configured to transmit the second command and the second address to the memory interface through the internal bus, and configured to control the buffer control circuit through the internal bus,

wherein each of the plurality of nonvolatile memory chips of the nonvolatile memory are configured to respectively transmit a ready/busy signal to the buffer chip through different respective ready/busy lines, and wherein the buffer chip is configured to respectively transmit the ready/busy signal from each of the plurality of nonvolatile memory chips to the memory controller through different respective second ready/busy lines.

2. The solid state drive of claim 1, wherein the memory controller further comprises a second RAM configured to temporarily store the first command, the first address, the second command, and the second address provided through the internal bus.

3. The solid state drive of claim 1, wherein the memory interface is connected with the buffer chip of the nonvolatile memory through a plurality of first input/output lines,

wherein the second command and the second address are transferred from the memory interface to the buffer chip through the plurality of first input/output lines, and

wherein the data is exchanged between the memory interface and the buffer chip through the plurality of first input/output lines.

4. The solid state drive of claim 3, wherein the buffer chip of the nonvolatile memory is connected in common to the plurality of nonvolatile memory chips of the nonvolatile memory through a plurality of second input/output lines,

wherein the second command and the second address are transmitted from the buffer chip to the plurality of nonvolatile memory chips of the nonvolatile memory through the plurality of second input/output lines, and

wherein the data is exchanged between the buffer chip and the plurality of nonvolatile memory chips of the nonvolatile memory through the plurality of second input/output lines.

5. The solid state drive of claim 1, wherein the memory interface is configured to transmit a data strobe signal, a read enable signal, a command latch enable signal, an address latch enable signal, a write enable signal and a write protection signal to the buffer chip through control lines.

6. The solid state drive of claim 1, wherein the buffer chip is configured to transmit a data strobe signal, a read enable signal, a command latch enable signal, an address latch enable signal, a write enable signal and a write protection signal in common to the plurality of nonvolatile memory chips of the nonvolatile memory through control lines.

7. The solid state drive of claim 1, wherein the buffer chip is configured to provide the plurality of nonvolatile memory chips with chip enable signals corresponding to the plurality of nonvolatile memory chips of the nonvolatile memory through chip enable lines.

8. The solid state drive of claim 1, further comprising a plurality of first nonvolatile memories,

wherein the nonvolatile memory and the plurality of first nonvolatile memories are configured to communicate with the memory interface through a first common channel, and

wherein each of the plurality of first nonvolatile memories has a same structure as the nonvolatile memory.

9. The solid state drive of claim 8, wherein at the first common channel, the nonvolatile memory and the plurality of first nonvolatile memories are configured to use, in common, input/output lines through which the second command, the second address, and the data are transmitted.

10. The solid state drive of claim 8, wherein at the first common channel, the nonvolatile memory and the plurality of first nonvolatile memories are configured to receive chip enable signals through separate chip enable lines.

11. The solid state drive of claim 8, further comprising a plurality of second nonvolatile memories,

wherein the plurality of second nonvolatile memories are configured to communicate with the memory interface through a second common channel, and

wherein each of the plurality of second nonvolatile memories has a same structure as the nonvolatile memory.

12. The solid state drive of claim 11, wherein the nonvolatile memory and the plurality of first nonvolatile memories are configured to communicate the second command, the second address and the data through first input/output lines of the first common channel, and

the plurality of second nonvolatile memories are configured to communicate the second command, the second address and the data through second input/output lines of the second common channel.

13. The solid state drive of claim 1, wherein each of the plurality of nonvolatile memory chips of the nonvolatile memory includes a plurality of cell strings arranged on a substrate along rows and columns, and

wherein each of the plurality of cell strings includes at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor sequentially stacked on the substrate in a direction perpendicular to the substrate.

14. The solid state drive of claim 1, wherein the memory interface is configured to transmit chip enable signals to the plurality of nonvolatile memory chips of the nonvolatile memory through a plurality of chip enable lines.

15. A solid state drive comprising:

a nonvolatile memory including a plurality of nonvolatile memory chips and a buffer chip;

a random access memory (RAM); and

a memory controller configured to control the nonvolatile memory and the RAM,

wherein the buffer chip is connected between the plurality of nonvolatile memory chips of the nonvolatile memory and the memory controller,

wherein each of the plurality of nonvolatile memory chips of the nonvolatile memory comprises a plurality of cell strings arranged on a substrate along rows and columns,

wherein each of the plurality of cell strings includes at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor sequentially stacked on the substrate in a direction perpendicular to the substrate, and

wherein each of the plurality of nonvolatile memory chips of the nonvolatile memory are configured to respectively transmit a ready/busy signal to the buffer chip through different respective ready/busy lines, and wherein the buffer chip is configured to respectively transmit the ready/busy signal from each of the plurality of the nonvolatile memory chips to the memory controller through different respective second ready/busy lines.