Cache memory bypass in a multi-core processor (MCP)

• US 9,886,389 B2
• Filed: 11/21/2008
• Issued: 02/06/2018
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Dumarot, Dan P., Duvalsaint, Karl J., Kim, Daeik, Kim, Moon J., Risi, Eugene B.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/276,072
• Publication Number:
  US 20100131717A1
• Time in Patent Office: 3,364 Days
• Field of Search: 711130, 711117, 711118, 711148, 709213
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Claims

1. A bypass memory system, comprising:

a first set of sub-memory elements mounted on a bus in a Multi-Core Processor (MCP) with hierarchical architecture;

a first memory unit mounted on the bus between the first set of sub-memory elements and the bus, the first memory unit being dedicated to the first set of sub-memory elements;

a first cache manager coupled to an input and an output of the first memory unit;

a second memory unit mounted on the bus between a second set of sub-memory elements and the bus, the second memory unit being on an equal hierarchical level to the first memory unit and being dedicated to the second set of sub-memory elements;

a main controller mounted on the bus and coupled to the first cache manager and a second cache manager and being operable to diagnose whether any of the first memory unit and the second memory unit is dead;

the first cache manager being operable to;

disassociate, in response to a diagnosis from the main controller that the first memory unit is dead, the first memory unit permanently from the first set of sub-memory units such that the first cache manager bypasses the first memory unit for any request originating from a first set of sub-processing elements to the first set of sub-memory elements that is operational and send the request to the second memory unit via the bus; and

the second cache manager coupled to an input and an output of the second memory unit, the second cache manager being operable to, couple, in response to the diagnosis from the main controller that the first memory unit is dead, the second memory unit to the first set of sub-memory units, allowing the coupled second cache memory to become an extension of a same level cache of the first memory unit, such that the second cache manager forwards the request from the first cache manager via the bus to the second memory unit for processing, and to manage operation between the second memory unit and the first set of sub-processing elements while the second memory unit continues to be dedicated to the second set of sub-processing units by sending the request to either of the following;

the second memory unit, and an externally located third memory unit in the case that the second memory unit fails to satisfy the request.

2. The bypass memory system of claim 1, the first memory unit and the second memory unit comprising virtualized cache memory units.

3. The bypass memory system of claim 2, the second cache manager being further operable to receive an additional request, bypass the second memory unit with the additional request, and send the additional request to at least one of the following:

the first memory unit;

or the third memory unit.

4. The bypass memory system of claim 1,

wherein the first set of sub-memory units is coupled to the first cache manager, and

the first set of sub-processing elements is coupled to the first set of sub-memory units.

5. The bypass memory system of claim 4, further comprising:

a second set of sub-memory units coupled to the second cache manager; and

the second set of sub-processing elements coupled to the second set of sub-memory units.

6. The bypass memory system of claim 1, the first cache manager further bypassing the first memory unit when the first memory unit is inoperable.

7. The bypass memory system of claim 1, the first cache manager being coupled to an input and an output of the first memory unit.

16. The bypass memory system of claim 1, further comprising:

a third set of sub-memory elements mounted on a bus in the Multi-Core Processor (MCP) with hierarchical architecture;

a third memory unit mounted on the bus between the third set of sub-memory elements and the bus, the third memory unit being dedicated to the third set of sub-memory elements;

a third cache manager coupled to an input and an output of the third memory unit;

a fourth memory unit mounted on the bus between a fourth set of sub-memory elements and the bus, the fourth memory unit being on an equal hierarchical level to the third memory unit and being dedicated to the fourth set of sub-memory elements;

the third cache manager being operable to;

disassociate, in response to a diagnosis from the main controller that the third memory unit is dead, the third memory unit permanently from the third set of sub-memory units such that the third cache manager bypasses the third memory unit for any request originating from a third set of sub-processing elements to the third set of sub-memory elements that is operational and send the request to the fourth memory unit via the bus; and

the fourth cache manager coupled to an input and an output of the fourth memory unit, the fourth cache manager being operable to;

disassociate, in response to a diagnosis from the main controller that the fourth set of sub-memory elements is dead, the fourth memory unit permanently from the fourth set of sub-memory elements and, dedicate, in response to the diagnosis from the main controller that the third memory unit is not operating correctly, the fourth memory unit to the third set of sub-memory units such that the fourth cache manager forwards the request from the third cache manager via the bus to the fourth memory unit for processing by sending the request to either of the following;

the fourth memory unit, and an externally located third memory unit in the case that the fourth memory unit fails to satisfy the request.

8. A cache bypass system, comprising:

a first cache memory unit mounted on a bus in a Multi-Core Processor (MCP) with hierarchical architecture between the first set of sub-memory elements and the bus, the first memory unit being dedicated to the first set of sub-memory elements;

a first cache manager coupled to an input and an output of the first cache memory unit;

a first set of sub-cache memory units coupled to the first cache manager such that the first cache memory unit and the first cache manager are disposed between the first set of sub-cache memory units and the bus;

a second cache memory unit mounted on the bus and disposed between a second set of sub-memory elements and the bus, the second memory unit being on an equal hierarchical level to the first memory unit and being dedicated to the second set of sub-memory elements;

a second cache manager coupled to an input and an output of the second cache memory unit;

a main controller mounted on the bus and coupled to the first cache manager and the second cache manager and being operable to diagnose whether any of the first memory unit and the second memory unit is dead;

the first cache manager and the second cache manager being operable to;

disassociate, in response to a diagnosis from the main controller that an associated cache memory unit is dead, the associated cache memory unit permanently from a dedicated set of sub-memory units such that the associated cache memory unit is bypassed for any a request originating from a first set of sub-processing elements to the dedicated set of sub-memory elements that is operational and send the request to different cache memory unit; and

wherein the first cache manager and second cache manager are each operable to couple, in response to the diagnosis from the main controller that the associated memory unit is dead, the different cache memory unit to the dedicated set of sub-memory units, allowing the coupled second cache memory to become an extension of a same level cache of the first memory unit, such that a request from either the dedicated set of sub-memory units or a set of sub-memory units that were preciously dedicated to the different cache memory unit are both managed by sending the request to either of the following;

the cache memory unit to which it is coupled, and an externally located different memory unit in the case the cache memory unit to which it is coupled to is unable to satisfy the request.

9. The cache bypass system of claim 8, further comprising the first set of sub-processing elements coupled to the first set of sub-cache memory units.

10. The cache bypass system of claim 8, further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.

11. A memory bypass method, comprising:

diagnosing, by a main controller mounted on a bus in a Multi-Core Processor (MCP) with hierarchical architecture and coupled to a first cache manager and a second cache manager, whether a first memory unit is dead;

receiving a first request on the first cache manager originating from a first set of sub-processing elements to a first set of sub-memory elements that is operational, the first cache manager coupled to an input and an output of the first memory unit, the first memory unit being dedicated to the first set of sub-memory elements and being disposed between the first set of sub-memory elements and the bus;

bypassing permanently, in response to a diagnosis from the main controller that the first memory unit is dead, the first memory unit by sending the first request from the first cache manager to the second cache manager, the second cache manager being coupled to the second memory unit, the second memory unit being coupled to the bus, being on an equal hierarchical level to the first memory unit, being dedicated to a second set of sub-memory elements, being on an equal hierarchical level as the first memory unit, and being disposed between the second set of sub-memory elements and the bus; and

wherein the second cache manager is operable to receive the request from the first cache manager, to couple the second memory unit to the first set of sub-memory units, allowing the coupled second cache memory to become an extension of a same level cache of the first memory unit, and to manage operation between the second memory unit and both the first set of sub-memory elements and the second set of sub-memory elements by sending the request to either of the following;

the second memory unit, and an externally located third memory unit in the case that the second memory unit fails to satisfy the request.

12. The memory bypass method of claim 11, the second request being received from the second set of sub-memory units coupled to the second memory unit.

13. The memory bypass method of claim 12, the first memory unit, the first set of sub-memory units, the second memory unit, and the second set of sub-memory units being cache memory units.

14. The memory bypass method of claim 11, further comprising sending a response to the first request from the second memory unit to an originator of the request.

15. The memory bypass method of claim 14, the response being sent via the second cache manager.