System and method for data-mask training in non-provisioned random access memory

• US 9,886,987 B1
• Filed: 12/30/2014
• Issued: 02/06/2018
• Est. Priority Date: 12/30/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Brahmadathan, Sandeep, Earl, Jeffrey Scott
• Primary Examiner(s): Cygiel, Gary W.
• Application Number:
  US14/585,621
• Time in Patent Office: 1,134 Days
• Field of Search: None
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A system and method providing timing alignment of a data mask (DM) signal with respect to a data strobe (DQS) signal for memory devices not designed for adjusting such alignment is provided. Alignment between data signals (DQ) and a DQS signal is first achieved during a first write training procedure where a data delay value is optimized for one of the DQS or DQ signals. Subsequently, using the optimum delay value from the first write training procedure, a second write training procedure is initiated. In the second write training procedure, timing alignment between the DM signal and the DQ signals is achieved by determining an optimal delay value of the DM signal relative to the DQS signal.

Claims

1. A method for data mask (DM) signal and data (DQ) signal timing alignment adjustment in transmission to a memory device, the method comprising:

performing write training of at least one DQ signal line using at least one known data pattern while maintaining a value of said DM signal at a constant value representing an unmasked condition to establish an optimal DQ delay value relative to a data strobe (DQS) signal; and

,

establishing an optimal DM delay value relative to said DQS signal for said DM signal by successively writing at least one known DQ signal data pattern using said optimal DQ delay value for transmission of DQ signals to said memory device while alternating said value of said DM signal to define a consistent sequence of alternating high and low values, to thereby provide a sequence of masked and unmasked bytes of said DQ signals during each write to said memory device, a DM signal delay value incrementally varied once for each of a plurality of consecutive writes to said memory device, said optimal DM delay value being established responsive to comparisons between said DQ signal data pattern and at least one retrieved data pattern from said memory device in correspondence with data masking in accordance with said alternating DM signal value sequence.

2. The method as recited in claim 1, where said DM signal is maintained at a zero value during said write training.

3. The method as recited in claim 1, where performing write training includes successively writing said known DQ signal data pattern while incrementally changing a delay value of said DQ signals relative to DQS signal.

4. The method as recited in claim 3, where said optimal DQ delay value is established as a mean of DQ delay values yielding alignment of leading and trailing edges of said DM signal relative to said DQS signal.

5. The method as recited in claim 1, where said optimal DQ delay value is established responsive to a comparison of said known DQ signal data pattern to a retrieved data pattern from said memory device subsequent to the writing thereto at a plurality of different delay values of said DQ signal relative to said DQS signal.

6. The method as recited in claim 1, where establishing an optimal DM delay value relative to said DQS signal includes:

determining a first delay value corresponding to a first edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in valid data being retrieved from said memory device for a first time;

determining a second delay value corresponding to a second edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in invalid data being retrieved from said memory device for a first time following retrieval of valid data; and

selecting a delay value intermediate the first and second delay values.

7. The method as recited in claim 6, where said selected intermediate delay value is a mean value between said first and second delay values.

8. A method for data mask (DM) signal and data (DQ) signal timing alignment adjustment in transmission to a memory device, the method comprising:

performing a first write training procedure of at least one DQ signal line using at least one known data pattern while maintaining a value of said DM signal at a constant value representing an unmasked condition to establish an optimal delay value of one of a data strobe (DQS) signal and DQ signals; and

,

performing a second write training procedure to establish an optimal DM delay value relative to said DQS signal for said DM signal by successively writing at least one known DQ signal data pattern using said optimal delay value of said one of a DQS signal and DQ signals established in said first write training procedure for transmission of DQ signals to said memory device while alternating said value of said DM signal to define a consistent sequence of alternating high and low values, to thereby provide a sequence of masked and unmasked bytes of said DQ signals during each write to said memory device, a DM signal delay value incrementally varied once for each of a plurality of consecutive writes to said memory device, said optimal DM delay value being established responsive to comparisons between said DQ signal data pattern and at least one retrieved data pattern from said memory device in correspondence with data masking in accordance with said alternating DM signal value sequence.

9. The method as recited in claim 8, where said optimal delay value of one of a DQS signal and DQ signals is an optimal DQ delay value.

10. The method as recited in claim 9, where performing said first write training procedure includes successively writing said known data pattern while incrementally changing a delay value of said DQ signals relative to DQS signal.

11. The method as recited in claim 10, where said optimal DQ delay value is established as a mean of DQ delay values yielding alignment of leading and trailing edges of said DM signal relative to said DQS signal.

12. The method as recited in claim 9, where said optimal DQ delay value is established responsive to a comparison of said known data pattern to a retrieved data pattern from said memory device subsequent to the writing thereto at a plurality of different delay values of said DQ signal relative to said DQS signal.

13. The method as recited in claim 8, where said DM signal is maintained at a zero value during said first write training procedure.

14. The method as recited in claim 8, where establishing an optimal DM delay value relative to said DQS signal includes:

determining a first delay value corresponding to a first edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in valid data being retrieved from said memory device for a first time;

determining a second delay value corresponding to a second edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in invalid data being retrieved from said memory device for a first time following retrieval of valid data; and

selecting a delay value intermediate the first and second delay values.

15. The method as recited in claim 14, where said selected intermediate delay value is a mean value between said first and second delay values.

16. A system for calibrating a data mask (DM) signal used to mask a selected portion of data transmitted to a memory device, comprising a memory controller including:

a control circuit for performing DM signal training in conjunction with the memory device;

a timing generator establishing a data strobe (DQS) signal;

a first delay circuit coupled to said control circuit and operable to selectively delay data (DQ) signals being transmitted to the memory device at any of a plurality of delay values in a range of available selectable delay values responsive a delay value signal from said control circuit; and

a second delay circuit coupled to said control circuit and operable to selectively delay a DM signal being transmitted to the memory device at any of a plurality of delay values in a range of available selectable delay values responsive a delay value signal from said control circuit;

wherein said control circuit is configured to perform a first write training procedure of at least one DQ signal line using at least one known data pattern while maintaining a value of said DM signal at a constant value representing an unmasked condition to establish an optimal delay value of one of said DQS signal and DQ signals, and then perform a second write training procedure to establish an optimal DM delay value relative to said DQS signal for said DM signal by successively writing at least one known DQ signal data pattern using said optimal delay value of said one of a DQS signal and DQ signals established in said first write training procedure for transmission of DQ signals to said memory device while alternating said value of said DM signal to define a consistent sequence of alternating high and low values, to thereby provide a sequence of masked and unmasked bytes of said DQ signals during each write to said memory device, a DM signal delay value incrementally varied once for each of a plurality of consecutive writes to said memory device, said control circuit performing comparisons between said DQ signal data pattern and at least one retrieved data pattern from said memory device in correspondence with data masking in accordance with said alternating DM signal value sequence to establish said optimal DM delay value.

17. The system as recited in claim 16, where said control circuit successively writes said known data pattern while incrementally changing a delay value of said DQ signals relative to said DQS signal while performing said first write training procedure.

18. The system as recited in claim 16, where said control circuit compares said known data pattern to a retrieved data pattern from said memory device subsequent to the writing thereto at a plurality of different delay values of one of said DQS signal and DQ signals relative to the other of said DQ signal and DQS signal to establish said optimal delay value of one of said DQS signal and DQ signals.

19. The system as recited in claim 16, where said control circuit in performing said second write training procedure determines (a) a first delay value corresponding to a first edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in valid data being retrieved from said memory device for a first time, and (b) a second delay value corresponding to a second edge alignment between said DM signal and said DQS signal when an incremental change in delay value results in invalid data being retrieved from said memory device for a first time following retrieval of valid data, said control circuit subsequently selects a delay value intermediate the first and second delay values to establish said optimal DM delay value relative to said DQS signal.

20. The system as recited in claim 16, where said control circuit successively writes said known data pattern while incrementally changing a delay value of said DQS signal relative to said DQ signals while performing said first write training procedure.