Method of forming SiOCN material layer and method of fabricating semiconductor device

• US 9,887,080 B2
• Filed: 12/08/2016
• Issued: 02/06/2018
• Est. Priority Date: 12/28/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Moon, Kang-hun, Tak, Yong-suk, Park, Gi-gwan
• Primary Examiner(s): Feliciano, Eliseo Ramos
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US15/372,434
• Publication Number:
  US 20170186603A1
• Time in Patent Office: 425 Days
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02208 the precursor containing a compound comprising Si
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02214 the compound comprising silicon and oxygen
• CPC Class Codes: H01L 21/02219 the compound comprising silicon and nitrogen
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.

Claims

1. A method of forming a SiOCN material layer, the method comprising:

supplying a silicon source onto a substrate;

supplying a carbon source onto the substrate;

supplying an oxygen source onto the substrate; and

supplying a nitrogen source onto the substrate,

wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof,

wherein the non-halogen silylamine includes a monosilylamine, a disilylamine, a disilylmethylamine, a disilylethylamine, a disilylisopropylamine, a disilyl-tert-butylamine, a tetrasilyldiamine, a diethylsilylamine, a diisopropylsilylamine, a di-tert-butylsilylamine, a bis(trimethylsilyl)amine, a bis(triethylsilyl)amine, or a mixture thereof,

wherein the silane compound is a material represented by one of the following formulae;

SiR¹R²R³R⁴,

R⁵R⁶R⁷Si—

SiR⁸R⁹R¹⁰,

wherein, in the above formulae;

R¹, R², R³, and R⁴ are each independently hydrogen, a hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C2-C10 alkenyl group, a C2-C10 alkynyl group, a C6-C10 aryl group, a C1-C10 monoalkylamino group, a C1-C10 dialkylamino group, or a C1-C10 trialkylamino group, and all of R¹, R², R³, and R⁴ are not hydrogen at the same time, and

R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are each independently hydrogen, a hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C2-C10 alkenyl group, a C2-C10 alkynyl group, a C6-C10 aryl group, a C1-C10 monoalkylamino group, a C1-C10 dialkylamino group, or a C1-C10 trialkylamino group, and all of R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are not hydrogen at the same time.

2. The method as claimed in claim 1, wherein:

the silicon source includes the non-halogen silylamine.

3. The method as claimed in claim 1, wherein:

the silicon source includes the silane compound.

4. The method as claimed in claim 1, wherein the silicon source has a molecular weight of about 45 to about 500.

5. The method as claimed in claim 1, further comprising supplying hydrogen onto the substrate.

6. The method as claimed in claim 5, wherein supplying hydrogen onto the substrate is performed at a temperature of about 400°

C. to about 700°

C.

7. The method as claimed in claim 1, wherein the SiOCN material layer has a halogen ion concentration of 0 atom % to about 0.2 atom %.

8. A method of fabricating a semiconductor device, the method comprising:

defining a fin-shaped active region on a semiconductor substrate such that the fin-shaped active region protrudes on the semiconductor substrate and extends in a first direction;

forming a gate electrode such that the gate electrode surrounds both sidewalls and an upper surface of the fin-shaped active region and extends in a direction intersecting the first direction;

forming a gate spacer on side walls of the gate electrode; and

forming impurity regions on both sides of the gate electrode,

wherein forming the gate spacer includes forming a SiOCN material layer using a non-halogen silylamine, a silane compound, or a mixture thereof as a silicon source.

9. The method as claimed in claim 8, wherein forming the SiOCN material layer includes:

supplying the silicon source onto the semiconductor substrate;

supplying a carbon source onto the semiconductor substrate;

supplying an oxygen source onto the semiconductor substrate; and

supplying a nitrogen source onto the semiconductor substrate.

10. The method as claimed in claim 9, wherein:

the silicon source is silyl amine,

the silicon source is the same as the nitrogen source, and

supplying the silicon source onto the semiconductor substrate and supplying nitrogen source onto the semiconductor substrate are performed at the same time.

11. The method as claimed in claim 9,

wherein the silicon source is a silane compound having a structure represented by one of the following formulae:

SiR¹R²R³R⁴, or

R⁵R⁶R⁷Si—

SiR⁸R⁹R¹⁰,

wherein, in the above formulae, R¹, R², R³, R⁴, R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are each independently hydrogen, a hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C2-C10 alkenyl group, a C2-C10 alkynyl group, a C6-C10 aryl group, a C1-C10 monoalkylamino group, a C1-C10 dialkylamino group, or a C1-C10 trialkylamino group;

all of R¹, R², R³, and R⁴ are not hydrogen at the same time; and

all of R⁵, R⁶, R⁷, R⁸, R⁹, and R¹⁰ are not hydrogen at the same time,

wherein the silicon source is the same as the carbon source, and

wherein supplying the silicon source onto the semiconductor substrate and supplying the carbon source onto the semiconductor substrate are performed at the same time.

12. The method as claimed in claim 8, wherein forming the gate spacer further includes forming a SiN material layer on the SiOCN material layer after the forming of the SioCN material layer.

13. The method as claimed in claim 8, wherein the SiOCN material layer has a dielectric constant of about 1 to about 5.5.

14. The method as claimed in claim 9, wherein:

forming the SiOCN material layer further includes supplying hydrogen onto the semiconductor substrate,

supplying the silicon source onto the semiconductor substrate, supplying the carbon source onto the semiconductor substrate, supplying the oxygen source onto the semiconductor substrate, and supplying the nitrogen source onto the semiconductor substrate form a deposition cycle, and

supplying hydrogen onto the semiconductor substrate is performed after the deposition cycle is performed two or more times.

15. A method of fabricating a semiconductor device, the method comprising:

forming active region on a semiconductor substrate;

forming a gate electrode on the active region;

forming a gate spacer on side walls of the gate electrode; and

forming impurity regions on both sides of the gate electrode,

wherein forming the gate spacer includes forming a SiOCN material by;

supplying a silicon source onto the substrate; and

supplying an oxygen source onto the substrate; and

wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof, provided that the silicon source does not include bis(tertiary-butylamino)silane.

16. The method as claimed in claim 15, wherein forming the gate spacer further includes supplying a nitrogen source onto the substrate, the nitrogen source being different from the silicon source.

17. The method as claimed in claim 15, wherein forming the gate spacer further includes supplying a carbon source onto the substrate, the carbon source being different from the silicon source.

18. The method as claimed in claim 15, wherein:

forming the gate spacer further includes;

supplying a nitrogen source onto the substrate, and

supplying a carbon source onto the substrate,

the nitrogen source is different from the silicon source, and

the carbon source is different from the silicon source.

19. A semiconductor device prepared according to the method as claimed in claim 15.