Integrated circuit assemblies with reinforcement frames, and methods of manufacture

• US 9,887,166 B2
• Filed: 05/26/2016
• Issued: 02/06/2018
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Katkar, Rajesh, Mirkarimi, Laura Wills, Sitaram, Arkalgud R., Woychik, Charles G.
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US15/165,837
• Publication Number:
  US 20160276294A1
• Time in Patent Office: 621 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/784 the substrate being a semiconductor body
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92225 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/04 : characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1615 : Shape
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/16176 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/1632 : Disposition
• CPC Class Codes: H01L 2924/164 : Material
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/16788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/1679 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Claims

1. An assembly comprising:

an interposer comprising a silicon substrate, the interposer comprising one or more first contact pads;

a plurality of modules attached to the interposer, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad;

a reinforcement frame comprising a silicon substrate comprising one or more cavities, the reinforcement frame being attached to the interposer, wherein at least part of each module is located in a corresponding cavity in the silicon substrate of the reinforcement frame, wherein for each module the corresponding cavity has a cavity surface overlying the module;

wherein the plurality of modules comprises a first module and a second module, and the cavity surface overlying the first module is deeper than the cavity surface overlying the second module;

wherein in operation of the assembly, the second module is to generate less heat than the first module.

2. The assembly of claim 1 wherein the cavity surfaces overlying the first and second modules are in the same cavity.

3. The assembly of claim 1 wherein the cavity surfaces overlying the first and second modules are in respective different cavities.

4. The assembly of claim 1 wherein the first and second modules have different heights.

5. The assembly of claim 1 wherein the first module is taller than the second module.

6. The assembly of claim 1 wherein the first and second modules have the same heights.

7. The assembly of claim 1 wherein the first and second modules are separated from the respective overlying cavity surfaces by gaps, and the gaps are the same.

8. The assembly of claim 1 wherein the first and second modules are separated from the respective overlying cavity surface by gaps, and the gaps have the same thermal resistance.

10. The assembly of claim 1 wherein the reinforcement frame is directly bonded to the interposer.

9. An assembly comprising:

an interposer comprising a silicon substrate, the interposer comprising one or more first contact pads;

a plurality of modules attached to the interposer, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad;

a reinforcement frame comprising a silicon substrate comprising one or more cavities, the reinforcement frame being attached to the interposer, wherein at least part of each module is located in a corresponding cavity in the silicon substrate of the reinforcement frame, wherein for each module the corresponding cavity has a cavity surface overlying the module;

wherein the plurality of modules comprises a first module and a second module, and the cavity surface overlying the first module is deeper than the cavity surface overlying the second module;

wherein the reinforcement frame comprises circuitry connected to contact pads located at tops of the first and second modules.

11. A manufacturing method comprising:

obtaining an interposer comprising a silicon substrate, the interposer comprising one or more first contact pads;

attaching a plurality of modules to the interposer, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad;

attaching, to the interposer, a reinforcement frame comprising a silicon substrate comprising one or more cavities, wherein the reinforcement frame is attached to the interposer so that at least part of each module is located in a corresponding cavity in the silicon substrate of the reinforcement frame, wherein for each module the corresponding cavity has a cavity surface overlying the module;

wherein the plurality of modules comprises a first module and a second module, and the cavity surface overlying the first module is deeper than the cavity surface overlying the second module;

wherein in operation of the assembly, the second module is to generate less heat than the first module.

12. The method of claim 11 wherein the reinforcement frame is attached to the interposer so that the cavity surfaces overlying the first and second modules are in the same cavity.

13. The method of claim 11 wherein the reinforcement frame is attached to the interposer so that the cavity surfaces overlying the first and second modules are in respective different cavities.

14. The method of claim 11 wherein the first module is taller than the second module.

15. The method of claim 11 further comprising, after attaching the first and second modules to the interposer but before attaching the reinforcement frame to the interposer, polishing a top surface of at least one module to improve uniformity of the module heights.

16. The method of claim 11 wherein the reinforcement frame is attached to the interposer so that the first and second modules are separated from the respective overlying cavity surfaces by gaps, and the gaps are the same.

17. The method of claim 11 wherein after said attaching the reinforcement frame to the interposer, the first and second modules are separated from the respective overlying cavity surface by gaps, and the gaps have the same thermal resistance.

18. A manufacturing method comprising:

obtaining an interposer comprising a silicon substrate, the interposer comprising one or more first contact pads;

attaching a plurality of modules to the interposer, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad;

attaching, to the interposer, a reinforcement frame comprising a silicon substrate comprising one or more cavities, wherein the reinforcement frame is attached to the interposer so that at least part of each module is located in a corresponding cavity in the silicon substrate of the reinforcement frame, wherein for each module the corresponding cavity has a cavity surface overlying the module;

wherein the plurality of modules comprises a first module and a second module, and the cavity surface overlying the first module is deeper than the cavity surface overlying the second module;

wherein the reinforcement frame comprises circuitry, and after said attaching the reinforcement frame to the interposer the circuitry is connected to contact pads located at tops of the first and second modules.