Integrating a planar field effect transistor (FET) with a vertical FET
First Claim
1. A semiconductor structure, comprising:
- a vertical field-effect transistor (FET) fabricated on a first semiconductor substrate; and
a planar FET fabricated on a second semiconductor substrate;
wherein the planar FET is integrated with the vertical FET;
wherein the vertical FET comprises;
a fin formed of a first semiconductor of the vertical FET;
a bottom source/drain (S/D) region for the first semiconductor, the bottom S/D region isolated from the first semiconductor substrate;
a spacer formed on the bottom S/D region by depositing spacer dielectric on the bottom S/D region;
a vertical gate perpendicular to and extending across the first semiconductor;
a top S/D region for the first semiconductor, the top S/D region including an epitaxy layer connected to the bottom S/D region via the fin; and
multiple contacts including a first S/D contact for the bottom S/D region, a second S/D contact for the top S/D region, and a gate contact for the vertical gate;
and wherein the planar FET comprises;
a second semiconductor;
an active region including a source region for the second semiconductor and a drain region for the second semiconductor;
a planar gate perpendicular to and extending across the second semiconductor; and
a gate dielectric, the gate dielectric isolating the second semiconductor from the planar gate.
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Accused Products
Abstract
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
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Citations
10 Claims
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1. A semiconductor structure, comprising:
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a vertical field-effect transistor (FET) fabricated on a first semiconductor substrate; and a planar FET fabricated on a second semiconductor substrate; wherein the planar FET is integrated with the vertical FET; wherein the vertical FET comprises; a fin formed of a first semiconductor of the vertical FET; a bottom source/drain (S/D) region for the first semiconductor, the bottom S/D region isolated from the first semiconductor substrate; a spacer formed on the bottom S/D region by depositing spacer dielectric on the bottom S/D region; a vertical gate perpendicular to and extending across the first semiconductor; a top S/D region for the first semiconductor, the top S/D region including an epitaxy layer connected to the bottom S/D region via the fin; and
multiple contacts including a first S/D contact for the bottom S/D region, a second S/D contact for the top S/D region, and a gate contact for the vertical gate;and wherein the planar FET comprises; a second semiconductor;
an active region including a source region for the second semiconductor and a drain region for the second semiconductor;a planar gate perpendicular to and extending across the second semiconductor; and a gate dielectric, the gate dielectric isolating the second semiconductor from the planar gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification