One-time programmable memory and method for making the same

• US 9,887,201 B2
• Filed: 08/29/2016
• Issued: 02/06/2018
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Kilopass Technology Incorporated (Synopsys Incorporated)
• Inventors: Luan, Harry Shengwen
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US15/250,831
• Publication Number:
  US 20170053927A1
• Time in Patent Office: 526 Days
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.

Claims

1. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate;

a dielectric layer formed over at least a portion of the buried bitline, the dielectric layer over the portion of the buried bitline having an even thickness;

insulating layers formed in the substrate on either side of the buried bitline, the insulating layers having a depth in the substrate greater than that of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer; and

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate wherein the channel region has no electrical interaction other than to the buried bitline or conductive gate.

2. The memory cell of claim 1 wherein the buried bitline has a severe graded first conductivity dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

3. The memory cell of claim 1 wherein the buried bitline has a first conductivity, and the conductive gate has a second conductivity different from the first conductivity.

4. The memory cell of claim 3 wherein the buried bitline has a severe graded first conductivity dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

5. The memory cell of claim 1 wherein the buried bitline has a first conductivity and the doped regions are of a second conductivity.

6. The memory cell of claim 1 wherein the buried bitline has a first conductivity and the doped regions are also of the first conductivity.

7. The memory cell of claim 1 wherein the insulating layers comprise shallow trench isolation.

8. The memory cell of claim 1 further comprising sidewall spacers disposed against the gate layer.

9. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline having a first conductivity;

a dielectric layer formed over at least a portion of the buried bitline;

insulating layers formed in the substrate on either side of the buried bitline, the insulating layers having a depth in the substrate greater than that of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer, the conductive gate has a second conductivity different from the first conductivity; and

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate wherein the channel region has no electrical interaction other than to the buried bitline or conductive gate.

10. The memory cell of claim 9 wherein the dielectric layer over the portion of the buried bitline has an even thickness.

11. The memory cell of claim 9 wherein the buried bitline has a severe graded first conductivity dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

12. The memory cell of claim 9 wherein the doped regions are of the second conductivity.

13. The memory cell of claim 9 wherein the doped regions are also of the first conductivity.

14. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline having a first conductivity and a severe graded first conductivity dopant concentration with a lower dopant concentration near a dielectric layer and a higher dopant concentration deeper in the substrate;

the dielectric layer formed over at least a portion of the buried bitline;

insulating layers formed in the substrate on either side of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer, the conductive gate having a second conductivity different from the first conductivity; and

wherein the channel region has no electrical interaction other than to the buried bitline or conductive gate.

15. The memory cell of claim 14 further comprising:

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate.

16. The memory cell of claim 15 wherein the buried bitline has the first conductivity and the doped regions are of the second conductivity.

17. The memory cell of claim 15 wherein the buried bitline has the first conductivity and the doped regions are also of the first conductivity.

18. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline having a first conductivity and a severe graded first conductivity dopant concentration with a lower dopant concentration near a dielectric layer and a higher dopant concentration deeper in the substrate;

the dielectric layer formed over at least a portion of the buried bitline;

insulating layers formed in the substrate on either side of the buried bitline, the insulating layers having a depth in the substrate greater than that of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer; and

wherein the channel region does not have electrical interaction other than to the buried bitline or conductive gate.

19. The method of claim 18 wherein the dielectric layer over the portion of the buried bitline has an even thickness.

20. The memory cell of claim 18 further comprising:

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate.

21. The memory cell of claim 20 wherein the buried bitline has the first conductivity and the doped regions are of a second conductivity.

22. The memory cell of claim 20 wherein the buried bitline has the first conductivity and the doped regions are also of the first conductivity.

23. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline having a first conductivity;

a dielectric layer formed over at least a portion of the buried bitline, the dielectric layer over the portion of the buried bitline having an even thickness;

insulating layers formed in the substrate on either side of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer, the conductive gate having a second conductivity different from the first conductivity; and

wherein the channel region does not have electrical interaction other than to the buried bitline or conductive gate.

24. The memory cell of claim 23 further comprising:

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate.

25. The memory cell of claim 24 wherein the buried bitline has the first conductivity and the doped regions are of the second conductivity.

26. The memory cell of claim 24 wherein the buried bitline has the first conductivity and the doped regions are also of the first conductivity.

27. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline having a first conductivity and a severe graded first conductivity dopant concentration with a lower dopant concentration near a dielectric layer and a higher dopant concentration deeper in the substrate;

the dielectric layer formed over at least a portion of the buried bitline, the dielectric layer over the portion of the buried bitline having an even thickness;

insulating layers formed in the substrate on either side of the buried bitline;

a conductive gate formed over the dielectric layer and a channel region under the conductive gate and dielectric layer; and

wherein the channel region does not have electrical interaction other than to the buried bitline or conductive gate.

28. The memory cell of claim 27 further comprising:

doped regions on either side of the conductive gate in the buried bitline but displaced from edges of the conductive gate.

29. The memory cell of claim 28 wherein the buried bitline has the first conductivity and the doped regions are of a second conductivity.

30. The memory cell of claim 28 wherein the buried bitline has the first conductivity and the doped regions are also of the first conductivity.