3D semiconductor device and structure

• US 9,887,203 B2
• Filed: 07/28/2016
• Issued: 02/06/2018
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): LE, DON P
• Application Number:
  US15/222,832
• Publication Number:
  US 20170162585A1
• Time in Patent Office: 558 Days
• Field of Search: 326 38
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM

Abstract

A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.

Claims

1. A 3D semiconductor device comprising:

a first layer comprising a first monocrystalline layer, said first layer comprising first logic cells;

a second layer comprising a monocrystalline semiconductor layer, said second layer overlying said first layer, said second layer comprising second transistors,

wherein said logic cells comprise a Look-Up-Table logic cell, and

wherein said second transistors are aligned to said first logic cells with less than 200 nm and greater than 0.1 nm alignment error.

2. The semiconductor device according to claim 1,

wherein said second layer is less than 2 microns and greater than 5 nm thick.

3. The semiconductor device according to claim 1,

wherein said device comprises an I/O circuit to connect said device to external devices, and

wherein said I/O circuit comprises at least one of said second transistors.

4. The semiconductor device according to claim 1,

wherein said device comprises a third layer comprising third transistors, and

wherein said third layer is disposed underneath said first layer.

5. The semiconductor device according to claim 1,

wherein said device comprises a thermally conductive path from said each of said first layer and said second layer to an external surface of said device.

6. The semiconductor device according to claim 1,

wherein said first layer comprises a repeating logic cell structure.

7. The semiconductor device according to claim 1, further comprising:

a connection path between at least one of said second transistors and at least one of said logic cells,

wherein said path comprises a through said second layer via, said through said second layer via has a radius of less than 400 nm and greater than 5 nm.

8. A 3D semiconductor device comprising:

a substrate comprising a first monocrystalline layer, said substrate comprising first transistors;

a second layer comprising a second monocrystalline semiconductor layer, said second layer overlying said first layer, said second layer comprising second transistors,

wherein said substrate comprises a programmable interconnect capable of forming at least two distinct interconnections between said first transistors, and

wherein said second transistors are aligned to said first transistors with less than 200 nm and greater than 0.1 nm alignment error.

9. The semiconductor device according to claim 8,

wherein said second layer is less than 2 microns and greater than 5 nm thick.

10. The semiconductor device according to claim 8,

wherein said device comprises an I/O circuit to connect said device to external devices, and

wherein said I/O circuit comprises at least one of said second transistors.

11. The semiconductor device according to claim 8,

wherein said device comprises a third monocrystalline layer comprising third transistors, and

wherein said third monocrystalline layer is underneath said first monocrystalline layer.

12. The semiconductor device according to claim 8,

wherein said device comprises a thermally conductive path from said each of said first monocrystalline layer and said second monocrystalline layer to an external surface of said device.

13. The semiconductor device according to claim 8,

wherein said first monocrystalline layer comprises a repeating logic cell structure.

14. The semiconductor device according to claim 8, further comprising:

a connection path between at least one of said second transistors and at least one of said first transistors,

wherein said path comprises a through said second monocrystalline layer via, said through said second monocrystalline layer via has a radius of less than 400 nm and greater than 5 nm.

15. A 3D semiconductor device comprising:

a first layer comprising a first monocrystalline layer, said first layer comprising first logic cells;

a second layer comprising a monocrystalline semiconductor layer, said second layer overlying said first layer, said second layer comprising second transistors,

wherein said first layer comprises a repeating structure of logic cells, and

wherein said second transistors are aligned to said first logic cells with less than 200 nm and greater than 0.1 nm alignment error.

16. The semiconductor device according to claim 15,

wherein said second layer is less than 2 microns and greater than 5 nm thick.

17. The semiconductor device according to claim 15,

wherein said device comprises an I/O circuit to connect said device to external devices, and

wherein said I/O circuit comprises at least one of said second transistors.

18. The semiconductor device according to claim 15,

wherein said device comprises a third monocrystalline layer comprising third transistors, and

wherein said third monocrystalline layer is underneath said first layer.

19. The semiconductor device according to claim 15,

wherein said device comprises a thermally conductive path from said each of said first layer and said second layer to an external surface of said device.

20. The semiconductor device according to claim 15, further comprising:

a connection path between at least one of said second transistors and at least one of said first transistors,

wherein said path comprises a through said second layer via, said through said second layer via has a radius of less than 400 nm and greater than 5 nm.