Method of making split gate non-volatile memory cell with 3D FinFET structure

• US 9,887,206 B2
• Filed: 03/08/2017
• Issued: 02/06/2018
• Est. Priority Date: 03/17/2015
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Su, Chien-Sheng, Yang, Jeng-Wei, Wu, Man-Tang, Chen, Chun-Ming, Tran, Hieu Van, Do, Nhan
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/453,829
• Publication Number:
  US 20170179141A1
• Time in Patent Office: 335 Days
• Field of Search: 438259
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Claims

1. A method of forming a non-volatile memory cell, comprising:

forming a pair of parallel trenches into a surface of a semiconductor substrate of a first conductivity type, resulting in a fin shaped upper surface portion between the trenches having a top surface and two side surfaces;

forming insulation material along the top surface and the two side surfaces;

forming spaced apart first and second regions of a second conductivity type different than the first conductivity type in the fin shaped upper surface portion, with a channel region extending between the first region and the second region;

wherein the channel region has a first portion that includes a first portion of the top surface and first portions of the two side surfaces, and has a second portion that includes a second portion of the top surface and second portions of the two side surfaces,

forming a conductive floating gate that includes;

a first portion that extends along and is insulated from the first portion of the top surface,

a second portion that extends along and is insulated from the first portion of one of the two side surfaces, and

a third portion that extends along and is insulated from the first portion of the other of the two side surfaces;

forming a conductive control gate that includes;

a first portion that extends along and is insulated from the second portion of the top surface,

a second portion that extends along and is insulated from the second portion of one of the two side surfaces,

a third portion that extends along and is insulated from the second portion of the other of the two side surfaces,

a fourth portion that extends up and over and is insulated from at least some of the floating gate first portion,

a fifth portion that extends out and over and is insulated from at least some of the floating gate second portion, and

a sixth portion that extends out and over and is insulated from at least some of the floating gate third portion.

2. The method of claim 1, wherein the forming of the pair of trenches includes:

forming a block of material over the surface of the substrate;

etching portions of the substrate adjacent to the block of material leaving the fin shaped upper surface portion underneath the block of material.

3. The method of claim 2, wherein the forming of the block of material includes:

forming a layer of material on the surface of the substrate;

forming a second block of material on the layer of material;

forming a spacer of material on the layer of material and along a side surface of the second block of material;

removing the second block of material;

etching portions of the layer of material adjacent to the spacer of material leaving the block of material underneath the spacer of material.

4. The method of claim 2, wherein the forming of the block of material includes:

forming a layer of material on the surface of the substrate;

forming photo resist over the layer of material;

performing a photolithography exposure and etch to selectively remove portions of the photo resist leaving a block of the photo resist on the layer of material;

etching portions of the layer of material adjacent to the block of photo resist leaving the block of material underneath the block of photo resist.

5. The method of claim 1, further comprising:

oxidizing a top surface of the floating gate to form oxidized polysilicon such that the top surface of the floating gate becomes sloping and terminates in a sharp edge that faces and is insulated from the control gate.