Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches

• US 9,887,240 B2
• Filed: 02/13/2017
• Issued: 02/06/2018
• Est. Priority Date: 11/17/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Shimabukuro, Seiji, Mine, Teruyuki, Ogawa, Hiroyuki, Takeguchi, Naoki
• Primary Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US15/430,888
• Publication Number:
  US 20170154925A1
• Time in Patent Office: 358 Days
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0009 RRAM elements whose operation depends upon chemical change
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 : Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/063 : by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/8822 : Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Claims

1. A method of fabricating a non-volatile data storage device comprising:

providing a substrate having control elements monolithically integrated therein;

providing above the substrate as a first structure, a three dimensional arrangement of non-volatile storage elements, and alternating horizontally extending layers of conductive word line layers and insulative layers;

providing above the substrate and below the first structure, material layers for forming a three dimensional arrangement of vertically oriented, bit line selector devices, where the provided material layers can be patterned so that each of the formable, vertically oriented bit line selector devices has a respective output terminal and a respective control terminal;

providing above the substrate and below the formable control terminals of the formable bit line selector devices, a plurality of spaced apart global bit lines;

patterning the alternating layers of conductive word line layers and insulative layers so as to form spaced apart pillars each having the alternating layers of conductive word lines and insulation, the pillars having respective vertically extending sidewalls;

depositing vertically extending films of memory cell forming material on the sidewalls of the pillars;

depositing vertically extending films of bit line forming conductive material on sidewalls of the deposited films of memory cell forming material, the bit line forming films also extending horizontally at respective bottoms of the bit line forming films so as to continue one into the next, the respective bottoms of the bit line forming films making electrical coupling with the formable output terminals of corresponding ones of the formable, vertically oriented bit line selector devices respectively disposed below the respective films of memory cell forming material;

creating electrically isolating separations between the deposited films of bit line forming conductive material so as to form vertically extending individual bit lines such that each individual bit line is electrically isolated from adjacent other individual bit lines extending vertically along adjacent vertically extending sidewalls of adjacent pillars; and

creating electrically isolating separations in the material layers provided for forming the formable, vertically oriented bit line selector devices so as to thereby define individual output terminals for respective ones of the vertically oriented bit line selector devices, the defined individual output terminals respectively connecting to respective ones of the vertically extending individual bit lines formed above the defined individual output terminals.

2. The method of fabricating of claim 1 and further comprising:

filling gaps between the adjacent and isolated from one another individual bit lines with an insulative gap filling material.

3. The method of fabricating of claim 1 wherein the memory cell forming material comprises a Hafnium Oxide.

4. The method of fabricating of claim 1 and further comprising:

attaching respective vertically extending and resistance lowering layers to the respective deposited and vertically extending films of bit line forming conductive material, the resistance lowering layers comprising at least one of a conductive material having a lower resistivity than that of the bit line forming conductive material and a material that can react with the bit line forming conductive material to thereby form a vertically extending reaction product layer having a lower resistivity than that of the bit line forming conductive material.

5. The method of claim 4 wherein:

the conductive material of the resistance lowering layers includes a metal.

6. The method of claim 4 wherein:

the reaction product layer includes a silicide.

7. The method of claim 1 wherein:

the memory cell forming material comprises a reversible resistance-switching material.

8. The method of claim 1 wherein:

said patterning of the alternating layers to form spaced apart pillars causes the respective output terminals of pairs of successive bit line selector devices to be disposed in areas between successive ones of the pillars and causes the respective control terminals of such pairs of successive bit line selector devices to be disposed in areas under the successive ones of the pillars.

9. The method of claim 1 wherein:

said patterning of the alternating layers to form spaced apart pillars is preceded by formation of conductive etch stops on top of the respective output terminals of the bit line selector devices, the etch stops functioning as stops for an anisotropic etch that forms said spaced apart pillars.

10. The method of claim 9 wherein:

said conductive etch stops include TiN.

11. The method of claim 9 wherein:

said depositing of the vertically extending films of bit line forming conductive material causes the films of bit line forming conductive material to contact corresponding ones of the conductive etch stops.

12. The method of claim 11 wherein:

said creating of the electrically isolating separations between the deposited films of bit line forming conductive material is followed by an anisotropic deep etch that cuts through the conductive etch stops.

13. The method of claim 12 wherein:

said anisotropic deep etch further cuts through a first material layer forming the respective output terminals of the vertically oriented, bit line selector devices; and

said anisotropic deep etch further cuts into a second material layer, below the first material layer and forming respective channel regions of the vertically oriented, bit line selector devices.

14. The method of claim 13 wherein:

said anisotropic deep etch does not cut through a third material layer, below the second material layer and forming respective input terminals of respective ones of the vertically oriented, bit line selector devices, whereby the respective input terminals of respective ones of the vertically oriented, bit line selector devices remain connected to one another.

15. The method of claim 14 wherein:

the third material layer includes an N-type semiconductive material;

the second material layer includes a P-type semiconductive material; and

the first material layer includes an N-type semiconductive material.

16. The method of claim 14 wherein:

said providing of the spaced apart global bit lines is followed by coupling of the third material layer of in line ones of the vertically oriented, bit line selector devices to a corresponding one of the global bit lines.

17. The method of claim 16 wherein:

the global bit lines include a conductive metal and the third material layer includes an N+doped semiconductive material making ohmic contact with the conductive metal.

18. The method of claim 12 and further comprising:

after said anisotropic deep etch, filling a deep trench formed by the anisotropic deep etch with a dielectric filler material.

19. A method of fabricating a non-volatile data storage device comprising:

forming above a substrate, a first material layer for defining source regions of vertically oriented, bit line selector devices;

forming above the first material layer, a plurality of spaced apart pillars each having alternating layers of conductive word lines and insulation, the pillars having respective vertically extending sidewalls;

forming above the first material layer and under the pillars, spaced apart pairs of conductive selector lines that each function as a control terminal for a respective one of the bit line selector devices;

forming above the first material layer and between areas occupied by the pillars, a second material layer for defining channel regions of the vertically oriented, bit line selector devices, the defined channel regions being disposed for capacitive coupling to respective adjacent ones of the conductive selector lines;

forming above the second material layer and between areas occupied by the pillars, a third material layer for defining drain regions of the vertically oriented, bit line selector devices;

forming above the third material layer and between areas occupied by the pillars, an etch stop material;

depositing a film of memory cell forming material on the sidewalls of the pillars and above the etch stop material; and

depositing a film of bit line forming conductive material on the deposited film of memory cell forming material.

20. The method of claim 19 and further comprising:

etching through the deposited film of memory cell forming material in areas between those occupied by the pillars;

etching through the deposited film of bit line forming conductive material in the areas between those occupied by the pillars; and

performing a deep etch cutting through the etch stop material and into the third material layer that defines the drain regions of the vertically oriented, bit line selector devices.