Array substrate, display device, and method for manufacturing array substrate

• US 9,887,255 B2
• Filed: 05/13/2015
• Issued: 02/06/2018
• Est. Priority Date: 04/10/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Xu, Xiangyang
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US14/785,978
• Publication Number:
  US 20170148862A1
• Time in Patent Office: 1,000 Days
• Field of Search: None
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate comprises a base substrate, a light-absorbing layer, and a bottom-gate thin film transistor unit arranged in sequence, wherein a projection of the light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of the bottom-gate thin film transistor unit. According to the present disclosure, the ambient light can be prevented from irradiating the metal layers of the bottom-gate thin film transistor unit effectively in the case that the brightness of the display panel is not reduced.

Claims

1. A display device, comprising:

an array substrate, wherein said array substrate comprises;

a base substrate;

a light-absorbing layer arranged on said base substrate; and

a bottom-gate thin film transistor unit arranged on said light-absorbing layer,

wherein a projection of said light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of said bottom-gate thin film transistor unit;

a passivation layer arranged on said array substrate;

a pixel electrode layer arranged on said passivation layer;

a pixel insulation layer arranged on said pixel electrode layer;

an organic layer arranged on said pixel insulation layer;

a cathode metal layer arranged on said organic layer; and

a packaging cover arranged on said cathode metal layer.

2. The display device according to claim 1, wherein said light-absorbing layer is an organic light-absorbing layer.

3. The display device according to claim 2, further comprising:

a passivation layer arranged on said array substrate;

a pixel electrode layer arranged on said passivation layer;

a pixel insulation layer arranged on said pixel electrode layer;

an organic layer arranged on said pixel insulation layer;

a cathode metal layer arranged on said organic layer; and

a packaging cover arranged on said cathode metal layer.

4. The display device according to claim 1, wherein said bottom-gate thin film transistor unit comprises:

said gate metal layer arranged on said light-absorbing layer;

a gate insulation layer arranged on said gate metal layer;

an active layer arranged on said gate insulation layer;

an etch-proof layer arranged on said active layer, said etch-proof layer being provided with a first via hole and a second via hole; and

said source metal layer and said drain metal layer arranged on said etch-proof layer, wherein said source metal layer and said drain metal layer are connected with said active layer through said first via hole and said second via hole respectively.

5. The display device according to claim 4, further comprising:

a passivation layer arranged on said array substrate;

a pixel electrode layer arranged on said passivation layer;

a pixel insulation layer arranged on said pixel electrode layer;

an organic layer arranged on said pixel insulation layer;

a cathode metal layer arranged on said organic layer; and

a packaging cover arranged on said cathode metal layer.

6. The display device according to claim 1, wherein the projection of said light-absorbing layer further covers the active layer of said bottom-gate thin film transistor unit.

7. The display device according to claim 6, wherein said light-absorbing layer is an organic light-absorbing layer.

8. The display device according to claim 6, wherein said bottom-gate thin film transistor unit comprises:

said gate metal layer arranged on said light-absorbing layer;

a gate insulation layer arranged on said gate metal layer;

an active layer arranged on said gate insulation layer;

an etch-proof layer arranged on said active layer, said etch-proof layer being provided with a first via hole and a second via hole; and

said source metal layer and said drain metal layer arranged on said etch-proof layer, wherein said source metal layer and said drain metal layer are connected with said active layer through said first via hole and said second via hole respectively.

9. A method for manufacturing an array substrate, comprising:

providing a base substrate; and

forming a light-absorbing layer and a bottom-gate thin film transistor unit on said base substrate, so that a projection of said light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of said bottom-gate thin film transistor unit;

wherein forming a light-absorbing layer and a bottom-gate thin film transistor unit on said base substrate comprises forming said light-absorbing layer and said gate metal layer on said base substrate, and forming said light-absorbing layer and said gate metal layer on said base substrate comprises;

depositing a light-absorbing layer and a gate metal layer on said base substrate in sequence;

coating said gate metal layer with photoresist;

exposing and developing said photoresist with a gray-tone photomask or a half-tone photomask so as to form an unexposed photoresist profile, a partly exposed photoresist profile, and a totally exposed region;

removing a gate metal layer and a light-absorbing layer bare outside the photoresist through a first etching procedure;

removing the photoresist outside said unexposed photoresist profile through a first ashing procedure;

removing the gate metal layer outside said unexposed photoresist profile through a second etching procedure; and

removing residual photoresist through a second ashing procedure.

10. The method according to claim 9, wherein forming a light-absorbing layer and a bottom-gate thin film transistor unit on said base substrate further comprises:

forming a gate insulation layer on said gate metal layer;

forming an active layer on said gate insulation layer;

forming an etch-proof layer on said active layer, and forming a first via hole and a second via hole in said etch-proof layer; and

forming said source metal layer and said drain metal layer on said etch-proof layer, and connecting said source metal layer and said drain metal layer with said active layer through said first via hole and said second via hole respectively.

11. The method according to claim 9, wherein exposing and developing said photoresist with a gray-tone photomask or a half-tone photomask so as to form an unexposed photoresist profile, a partly exposed photoresist profile, and a totally exposed region specifically comprises:

exposing said photoresist with a gray-tone photomask or a half-tone photomask so as to form an unexposed region, a partly exposed region, and said totally exposed region; and

removing the photoresist in said totally exposed region totally, removing the photoresist in said partly exposed region partly so as to form said partly exposed photoresist profile, and reserving the photoresist in said unexposed region so as to form said unexposed photoresist profile through developing.

12. The method according to claim 11, wherein forming a light-absorbing layer and a bottom-gate thin film transistor unit on said base substrate further comprises:

forming a gate insulation layer on said gate metal layer;

forming an active layer on said gate insulation layer;

forming an etch-proof layer on said active layer, and forming a first via hole and a second via hole in said etch-proof layer; and

forming said source metal layer and said drain metal layer on said etch-proof layer, and connecting said source metal layer and said drain metal layer with said active layer through said first via hole and said second via hole respectively.