FinFETs and methods for forming the same

• US 9,887,274 B2
• Filed: 05/02/2016
• Issued: 02/06/2018
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Fan, Chun-Hsiang, Perng, Tsu-Hsiu, Liu, Chi-Kang, Li, Yung-Ta, Tsai, Ming-Huan, Wann, Clement Hsingjen, Liu, Chi-Wen
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/144,360
• Publication Number:
  US 20160247900A1
• Time in Patent Office: 645 Days
• Field of Search: None
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/34 the imperfections being on the surface
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

Claims

1. A method comprising:

forming trenches in a semiconductor substrate to form a fin;

depositing an insulating material within the trenches;

removing a portion of the insulating material to expose sidewalls of the fin;

recessing a portion of the exposed sidewalls of the fin to form a plurality of recessed surfaces on the exposed sidewalls of the fin, the plurality of recessed surfaces having a stairstep profile, adjacent recessed surfaces of the plurality of recessed surfaces being separated by a lattice shift;

depositing a gate dielectric on the recessed portion of the sidewalls of the fin, the gate dielectric extending along each of the recessed surfaces of the stairstep profile; and

depositing a gate electrode on the gate dielectric.

2. The method of claim 1, further comprising:

forming a dummy dielectric on the fin;

forming a dummy gate on the dummy dielectric; and

removing the dummy gate and the dummy dielectric, the recessing being performed after removing the dummy gate and the dummy dielectric.

3. The method of claim 1, wherein the recessing comprises using a wet etch.

4. The method of claim 1, wherein the recessing comprises using a dry etch.

5. The method of claim 1, wherein the recessing comprises using an anneal.

6. The method of claim 1, wherein a portion of the adjacent recessed surfaces of the plurality of recessed surfaces are separated by multiple lattice shifts.

7. The method of claim 1, further comprising recessing a portion of a top surface of the fin.

8. A method comprising:

forming a plurality of fins protruding from a semiconductor substrate, wherein a top surface of the plurality of fins extends farther from the semiconductor substrate than a top surface of an insulating material adjacent the plurality of fins;

reshaping first portions of respective sidewalls of each respective fin of the plurality of fins to have a first stairstep profile, the first portions extending from the top surface of the insulating material to the top surface of the respective fin;

forming at least one gate dielectric contacting the reshaped first portions of the plurality of fins; and

forming at least one gate electrode over the at least one gate dielectric.

9. The method of claim 8, wherein a portion of the first stairstep profile comprises one or more lattice shifts separating adjacent planar surfaces.

10. The method of claim 8, wherein the reshaping comprises using a wet etch.

11. The method of claim 8, wherein the reshaping comprises using a dry etch.

12. The method of claim 8, wherein the reshaping comprises using an anneal.

13. The method of claim 8, wherein the reshaping also comprises reshaping second portions of the respective sidewalls of each respective fin of the plurality of fins to have a second stairstep profile.

20. The method of claim 8, wherein the at least one gate dielectric extends along the first stairstep profile of the reshaped portions of each respective fin of the plurality of fins.

14. A method comprising:

forming a fin in a substrate, wherein the fin is adjacent an isolation region;

reforming a first exposed surface of the fin into a second exposed surface, wherein the second exposed surface has greater surface roughness than the first exposed surface, wherein the second exposed surface has a stairstep profile, wherein a channel region of the fin comprises the second exposed surface;

forming a dielectric on the second exposed surface, the dielectric physically contacting the stairstep profile of the second exposed surface; and

forming a gate electrode on the dielectric.

15. The method of claim 14, wherein reforming the first exposed surface into a second exposed surface comprises a wet etch, a dry etch, an anneal, or a combination thereof.

16. The method of claim 14, wherein the second exposed surface of the fin extends past the channel region of the fin.

17. The method of claim 14, wherein the second exposed surface of the fin comprises a topmost surface of the fin.

18. The method of claim 14, further comprising removing a portion of the isolation region to expose the first exposed surface of the fin.

19. The method of claim 14, further comprising forming a source/drain region adjacent the channel region of the fin.