Semiconductor device having low impedance and method of manufacturing the same

• US 9,887,286 B2
• Filed: 09/14/2015
• Issued: 02/06/2018
• Est. Priority Date: 12/12/2014
• Status: Active Grant

• Current Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Original Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Inventors: Chun, Dae Hwan, Lee, Jong Seok, Park, Junghee, Hong, Kyoung-Kook, Jung, Youngkyun
• Primary Examiner(s): Nicely, Joseph C
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US14/853,459
• Publication Number:
  US 20160172483A1
• Time in Patent Office: 876 Days
• Field of Search: 257331
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

The present inventive concept relates to a semiconductor device, and more particularly to a semiconductor device that can increase the amount of current by reducing impedance, and a method of manufacturing the semiconductor device.

A semiconductor device comprises an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; an n+ region disposed on the n− type epitaxial layer; first and second trenches disposed in the n− type epitaxial layer and the n+ region; first and second gate insulating layers disposed inside the first and second trenches, respectively; first and second gate electrodes disposed on the first and second gate insulating layers, respectively; a p-type region disposed on two sides of one of the first and second trenches; an oxidation film disposed on the first and second gate electrodes; a source electrode disposed on the n+ region and the oxidation film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein a first channel is disposed on two sides of the first trench and a second channel is disposed on two sides of the second trench.

Claims

1. A semiconductor device comprising:

an n−

type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate;

an n+ region disposed on the n−

type epitaxial layer;

first and second trenches disposed in the n−

type epitaxial layer and the n+ region;

first and second gate insulating layers disposed inside the first and second trenches, respectively;

first and second gate electrodes disposed on the first and second gate insulating layers, respectively;

a p-type region disposed on two sides of one of the first and second trenches;

an oxidation film disposed on the first and second gate electrodes;

a source electrode disposed on the n+ region and the oxidation film; and

a drain electrode disposed on a second surface of the n+ type silicon carbide substrate,

wherein a first channel is disposed on two sides of the first trench and a second channel is disposed on two sides of the second trench,

wherein the first and second gate insulating layers have different thicknesses, and

wherein the first and second gate electrodes have different depths.

2. The semiconductor device of claim 1, wherein the source electrode is in contact with the n+ region and the p-type region.

3. The semiconductor device of claim 1, wherein a bottom surface of the source electrode is alternately in contact with a top surface of the n+ region and a top surface of the p-type region.

4. The semiconductor device of claim 1, wherein the p-type region is disposed on two sides of the second trench, and the first channel is an accumulation-layer channel and the second channel is an inversion-layer channel.

5. The semiconductor device of claim 1, wherein the first and second trenches have different depths.