Memory management method

• US 9,891,854 B2
• Filed: 11/11/2016
• Issued: 02/13/2018
• Est. Priority Date: 06/17/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Munetoh, Seiji, Ohba, Nobuyuki
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US15/349,391
• Publication Number:
  US 20170075618A1
• Time in Patent Office: 459 Days
• Field of Search: 711101, 711103, 711105
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell

Abstract

A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.

Claims

1. A method for managing main memory comprising DRAM and NVRAM in a computer depending on a transition of an operation state of the computer, the method comprising:

upon start of the computer, loading at least one of a first program and a first data into the DRAM, and loading at least one of a second program and a second data into the NVRAM;

in a state transition from a normal operation of the computer to a suspend state of the computer, moving the first data in the DRAM to the NVRAM on a page basis;

in a state transition from the suspend state of the computer to the normal operation of the computer, reading the first data from the NVRAM on a page basis for program execution by the computer;

in the case where a first data write to the NVRAM on a page basis occurs while reading the first data from the NVRAM on a page basis, stopping the first data write, and moving the first data in a data area of the NVRAM subjected to the first data write, to the DRAM on a page basis;

performing the first data write on a page basis to the DRAM to which the first data has been moved;

detecting a first use state of the DRAM; and

moving a page in the DRAM that has not been read for a first time and has not been written for a second time to the NVRAM responsive to detecting the first use state of the DRAM.

2. The method according to claim 1, wherein detecting a first use state of the DRAM further comprises determining that an operating ratio of a processor in the computer is less than or equal to a predetermined value.

3. The method according to claim 1, wherein detecting a respective use state of the DRAM occurs at each first time interval.

4. The method according claim 1, wherein detecting a first use state of the DRAM further comprises determining that no input to the computer has been made for a predetermined time.

5. The method according to claim 1, wherein moving the first data in the DRAM to the NVRAM on a page basis includes updating a corresponding page table each time data is moved.

6. The method according to claim 1, wherein performing the first data write on a page basis to the DRAM to which the first data has been moved includes updating a corresponding page table each time data is written.

7. The method according to claim 1, wherein the operation state of the computer is an operation state conforming to the Advanced Configuration and Power Interface (ACPI) standard.

8. The method according to claim 1, wherein moving the first data in the DRAM to the NVRAM on a page basis in the state transition from the normal operation of the computer to the suspend state of the computer further comprises:

determining that the NVRAM has insufficient space to store the first data;

transferring a first portion of data in the NVRAM larger than the first data from the NVRAM to an external storage device; and

transferring the first data from the DRAM to the NVRAM in response to transferring the first portion of data from the NVRAM to the external storage device.

9. A computer program product for managing main memory comprising DRAM and NVRAM in a computer depending on a transition of an operation state of the computer, the computer program product comprising at least one computer readable non-transitory storage medium having computer readable program instructions thereon for execution by a processor, the computer readable program instructions comprising program instructions for:

upon start of the computer, loading at least one of a first program and a first data into the DRAM, and loading at least one of a second program and a second data into the NVRAM;

in a state transition from a normal operation of the computer to a suspend state of the computer, moving the first data in the DRAM to the NVRAM on a page basis;

in a state transition from the suspend state of the computer to the normal operation of the computer, reading the first data from the NVRAM on a page basis for program execution by the computer;

in the case where a first data write to the NVRAM on a page basis occurs while reading the first data from the NVRAM on a page basis, stopping the first data write, and moving the first data in a data area of the NVRAM subjected to the first data write, to the DRAM on a page basis;

performing the first data write on a page basis to the DRAM to which the first data has been moved;

detecting a first use state of the DRAM; and

moving a page in the DRAM that has not been read for a first time and has not been written for a second time to the NVRAM responsive to detecting the first use state of the DRAM.

10. The computer program product according to claim 9, wherein the program instructions further comprise program instructions for:

detecting a use state of respective instances of a page table stored in the DRAM;

determining, based on detecting the use state of respective instances of the page table stored in the DRAM, that a third data in the DRAM has not been read for a third time interval;

determining that the third time interval is greater than a threshold read time; and

moving the third data from the DRAM to the NVRAM responsive to determining that the third time interval is greater than the threshold read time.

11. A computer system for managing main memory comprising DRAM and NVRAM in a computer depending on a transition of an operation state of the computer, the computer system comprising:

at least one processor;

at least one computer readable memory;

at least one computer readable tangible, non-transitory storage medium; and

program instructions stored on the at least one computer readable tangible, non-transitory storage medium for execution by the at least one processor via the at least one computer readable memory,

wherein the at least one computer readable memory includes the main memory comprising DRAM and NVRAM, and

wherein the program instructions comprise program instructions for;

upon start of the computer, loading at least one of a first program and a first data into the DRAM, and loading at least one of a second program and a second data into the NVRAM;

in a state transition from a normal operation of the computer to a suspend state of the computer, moving the first data in the DRAM to the NVRAM on a page basis;

in a state transition from the suspend state of the computer to the normal operation of the computer, reading the first data from the NVRAM on a page basis for program execution by the computer;

in the case where a first data write to the NVRAM on a page basis occurs while reading the first data from the NVRAM on a page basis, stopping the first data write, and moving the first data in a data area of the NVRAM subjected to the first data write, to the DRAM on a page basis;

performing the first data write on a page basis to the DRAM to which the first data has been moved;

detecting a first use state of the DRAM; and

moving a page in the DRAM that has not been read for a first time and has not been written for a second time to the NVRAM responsive to detecting the first use state of the DRAM.

12. The computer system according to claim 11, further comprising an external storage device, wherein the moving the first data in the DRAM to the NVRAM on a page basis includes moving the first data in the DRAM to the external storage device.

13. The computer system according to claim 12, wherein the moving the first data in the DRAM to the NVRAM on a page basis includes updating a corresponding page table each time data is moved.

14. The computer system according to claim 11, wherein in the state transition from the normal operation of the computer to the suspend state of the computer, moving the first data in the DRAM to the NVRAM on a page basis further comprises moving a page table corresponding to the first data from the DRAM to the NVRAM responsive to moving the first data from the DRAM to the NVRAM.

15. The computer system according to claim 14, wherein moving the first data in the data area of the NVRAM subjected to the first data write to the DRAM on a page basis occurs responsive to moving the page table corresponding to the first data from the NVRAM to the DRAM.

16. The computer system according to claim 11, wherein the program instructions further comprise program instructions for:

detecting a use state of respective instances of a page table stored in the DRAM;

determining, based on detecting the use state of respective instances of the page table stored in the DRAM, that a third data in the DRAM has not been read for a third time interval;

determining that the third time interval is greater than a threshold read time; and

moving the third data from the DRAM to the NVRAM responsive to determining that the third time interval is greater than the threshold read time.