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Inter-core communication via uncore RAM

  • US 9,891,927 B2
  • Filed: 05/19/2014
  • Issued: 02/13/2018
  • Est. Priority Date: 08/28/2013
  • Status: Active Grant
First Claim
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1. A microprocessor, comprising:

  • one or more dies, each including a plurality of processing cores;

    an uncore random access memory (RAM) on each die, readable and writable by each of the die'"'"'s plurality of processing cores;

    wherein each core of the plurality of processing cores implements architectural instructions of an instruction set architecture of the microprocessor; and

    wherein each core comprises microcode configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores, said microcode handling at least one of the following;

    trans-core debug requests, power management, or dynamic multi-core microprocessor configuration;

    wherein the uncore RAM is not in an architectural user program address space of the microprocessor, and therefore the uncore RAM is inaccessible to user programs.

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