Inter-core communication via uncore RAM

• US 9,891,927 B2
• Filed: 05/19/2014
• Issued: 02/13/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Hooker, Rodney E., Gaskins, Stephan
• Primary Examiner(s): Pan, Daniel
• Application Number:
  US14/281,551
• Publication Number:
  US 20150067306A1
• Time in Patent Office: 1,366 Days
• Field of Search: 712 29, 712 32, 712 38, 712 39, 712227, 713323, 713155, 713164
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

Claims

1. A microprocessor, comprising:

one or more dies, each including a plurality of processing cores;

an uncore random access memory (RAM) on each die, readable and writable by each of the die'"'"'s plurality of processing cores;

wherein each core of the plurality of processing cores implements architectural instructions of an instruction set architecture of the microprocessor; and

wherein each core comprises microcode configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores, said microcode handling at least one of the following;

trans-core debug requests, power management, or dynamic multi-core microprocessor configuration;

wherein the uncore RAM is not in an architectural user program address space of the microprocessor, and therefore the uncore RAM is inaccessible to user programs.

2. The microprocessor of claim 1, wherein the microcode of each core of the plurality of processing cores is configured to implement a trusted platform module (TPM), wherein the microcode is configured such that only one of the plurality of processing cores implements the TPM at each instance of time, wherein the inter-core communication between the plurality of processing cores comprises a transfer of state of the TPM from a first of the plurality of processing cores to a second of the plurality of processing cores.

3. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores, in response to encountering an architectural instruction that instructs the microprocessor to invalidate the microprocessor'"'"'s cache memories, sends a message via the uncore RAM to each of the other plurality of processing cores to invalidate core-local cache memories.

4. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores sends a message via the uncore RAM to each of the other plurality of processing cores to dump a state of each of the other plurality of processing cores for debugging purposes.

5. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores sends a message via the uncore RAM to each of the other plurality of processing cores to apply a microcode patch.

6. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writes a microcode patch to the uncore RAM and each of the other plurality of processing cores reads the microcode patch from the uncore RAM.

7. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores, in response to encountering an architectural instruction that instructs the first core to disable itself, sends a message via the uncore RAM to each of the other plurality of processing cores to perform a query to determine which of the plurality of processing cores of the microprocessor are enabled.

8. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writes a value to the uncore RAM and each of the other plurality of processing cores reads the value from the uncore RAM; and

wherein each of the plurality of processing cores is configured to update a respective per-core-instantiated architecturally-visible storage resource with the value.

9. The microprocessor of claim 1, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writes a value to the uncore RAM indicating a number of processing cores of the microprocessor; and

wherein each of the plurality of processing cores is configured to read the value from the uncore RAM to perform an architectural instruction that requests the number of processing cores of the microprocessor.

10. A method to be performed by a microprocessor having one or more dies, each including a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the die'"'"'s plurality of processing cores, wherein each core of the plurality of processing cores implements architectural instructions of an instruction set architecture of the microprocessor and each core comprises microcode, the method comprising:

reading, by the microcode, to the uncore RAM;

writing, by the microcode, from the uncore RAM;

wherein said reading and writing accomplish inter-core communication between the plurality of processing cores, with said microcode handling at least one of the following;

trans-core debug requests, power management, or dynamic multi-core microprocessor configuration;

wherein the uncore RAM is not in an architectural user program address space of the microprocessor, and therefore the uncore RAM is inaccessible to user programs.

11. The method of claim 10, wherein the microcode of each core of the plurality of processing cores is configured to implement a trusted platform module (TPM), wherein the microcode is configured such that only one of the plurality of processing cores implements the TPM at each instance of time, wherein the inter-core communication between the plurality of processing cores comprises a transfer of state of the TPM from a first of the plurality of processing cores to a second of the plurality of processing cores.

12. The method of claim 10, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores, in response to encountering an architectural instruction that instructs the microprocessor to invalidate the microprocessor'"'"'s cache memories, sending a message via the uncore RAM to each of the other plurality of processing cores to invalidate core-local cache memories.

13. The method of claim 10, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores sending a message via the uncore RAM to each of the other plurality of processing cores to dump a state of each of the other plurality of processing cores for debugging purposes.

14. The method of claim 10, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores sending a message via the uncore RAM to each of the other plurality of processing cores to apply a microcode patch.

15. The method of claim 10, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writing a microcode patch to the uncore RAM and each of the other plurality of processing cores reading the microcode patch from the uncore RAM.

16. The method of claim 10, wherein the inter-core communication between the plurality of processing cores comprises:

a first of the plurality of processing cores, in response to encountering an architectural instruction that instructs the first core to disable itself, sending a message via the uncore RAM to each of the other plurality of processing cores to perform a query to determine which of the plurality of processing cores of the microprocessor are enabled.

17. The method of claim 10, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writing a value to the uncore RAM and each of the other plurality of processing cores reading the value from the uncore RAM; and

updating, by each of the plurality of processing cores, a respective per-core-instantiated architecturally-visible storage resource with the value.

18. The method of claim 10, wherein the inter-core communication between the plurality of processing cores further comprises:

a first of the plurality of processing cores writing a value to the uncore RAM indicating a number of processing cores of the microprocessor; and

reading, by each of the plurality of processing cores, the value from the uncore RAM to perform an architectural instruction that requests the number of processing cores of the microprocessor.

19. A computer program product encoded in at least one non-transitory computer usable medium executed by a computing device, the computer program product comprising:

computer usable program code embodied in said non-transitory computer readable medium, for specifying a microprocessor that comprises;

one or more dies, each including a plurality of processing cores; and

an uncore random access memory (RAM) on each die, readable and writable by each of the die'"'"'s plurality of processing cores;

wherein each core of the plurality of processing cores implements architectural instructions of an instruction set architecture of the microprocessor; and

wherein each core comprises microcode configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores, said microcode handling at least one of the following;

trans-core debug requests, power management, or dynamic multi-core microprocessor configuration;

wherein the uncore RAM is not in an architectural user program address space of the microprocessor, and therefore the uncore RAM is inaccessible to user programs.