Propagation of updates to per-core-instantiated architecturally-visible storage resource

• US 9,891,928 B2
• Filed: 08/09/2016
• Issued: 02/13/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): PAN, DANIEL H
• Application Number:
  US15/232,506
• Publication Number:
  US 20160349824A1
• Time in Patent Office: 553 Days
• Field of Search: 712 30- 40, 712224, 713375-601
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Claims

1. A microprocessor, comprising:

a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource;

wherein a first core of the plurality of processing cores is configured to;

encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction; and

in response to encountering the architectural instruction;

communicate an update message to all of the other of the plurality of processing cores;

provide the value to all of the other of the plurality of processing cores; and

update the respective architecturally-visible storage resource of the first core with the value;

wherein each core of all the other of the plurality of processing cores than the first core is configured to respond to the update message by updating the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction; and

wherein plurality of processing cores comprises at least three processing cores.

2. The microprocessor of claim 1,

wherein the first core is further configured to generate an interrupt request to each of the other of the plurality of processing cores, in response to encountering the architectural instruction;

and

wherein each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core in response to the interrupt request from the first core.

3. The microprocessor of claim 2,

wherein the first core is configured to disable interrupts in response to encountering the architectural instruction until after all of the plurality of processing cores have updated the respective architecturally-visible storage resource with the value;

and

each of the other of the plurality of processing cores is configured to disable interrupts in response to the interrupt request from the first core until after all of the plurality of processing cores have updated the respective architecturally-visible storage resource with the value.

4. The microprocessor of claim 2, wherein the interrupt request comprises a non-architectural interrupt request.

5. The microprocessor of claim 1, further comprising:

a hardware semaphore shared by the plurality of processing cores; and

wherein the first core is further configured to obtain ownership of the hardware semaphore prior to providing the value.

6. The microprocessor of claim 1, wherein each of the plurality of processing cores comprises microcode, where the microcode of the first core is configured to provide the value, wherein the microcode of each of the other of the plurality of processing cores is configured to update the respective architecturally-visible storage resource with the value.

7. The microprocessor of claim 1, further comprising:

a memory shared by the plurality of processing cores; and

wherein to provide the value, the first core is configured to write the value to the shared memory.

8. The microprocessor of claim 1, further comprising:

an uncore control unit shared by the plurality of processing cores; and

wherein each core of the plurality of processing cores is configured to make a synchronization request to the uncore control unit prior to updating the respective architecturally-visible storage resource of the core with the value.

9. The microprocessor of claim 1, further comprising:

an uncore control unit shared by the plurality of processing cores;

wherein each core of the plurality of processing cores is configured to make a synchronization request to the uncore control unit after updating the respective architecturally-visible storage resource of the core with the value; and

wherein each of the plurality of processing cores is configured to wait to enable interrupts until all of the plurality of processing cores have made the synchronization request.

10. The microprocessor of claim 1, wherein the architecturally-visible storage resource comprises an x86 architecture memory type range register (MTRR).

11. The microprocessor of claim 10, wherein the MTRR comprises an x86 architecture system management range register (SMRR).

12. The microprocessor of claim 10,

wherein the MTRR comprises an x86 architecture variable range MTRR comprising a base register and a mask register, wherein the mask register includes a valid bit;

wherein the first core, in response to encountering the architectural instruction, is further configured to;

if the architectural instruction specifies the mask register;

provide a current value of the base register of the first core to each of the other of the plurality of processing cores and set a flag readable by each of the other of the plurality of processing cores;

if the architectural instruction specifies the base register and the valid bit of the mask register of the first core is currently set;

provide a current value of the mask register of the first core to each of the other of the plurality of processing cores and set the flag; and

otherwise;

clear the flag; and

wherein to the update the value, each of the plurality of processing cores updates both the base register and the mask register if the flag is set, and otherwise update only the base register or mask register as specified by the architectural instruction.

13. The microprocessor of claim 1, wherein the architecturally-visible storage resource comprises an x86 architecture model specific register (MSR).

14. The microprocessor of claim 1, wherein each of the plurality of processing cores is configured to operate both as the first core and as one of the other of the plurality of processing cores.

15. A method to be performed in a microprocessor having a plurality of processing cores, wherein each core of the plurality of processing cores instantiates a respective architecturally-visible storage resource, the method comprising:

encountering, by a first core of the plurality of processing cores, an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction;

communicating an update message from the first core to all of the other of the plurality of processing cores, in response to said encountering the architectural instruction;

providing, by the first core, the value to all of the other of the plurality of processing cores, in response to said encountering the architectural instruction;

updating, by the first core, the respective architecturally-visible storage resource of the first core with the value, in response to said encountering the architectural instruction; and

updating, by each core of all the other of the plurality of processing cores than the first core in response to the update message, the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction; and

wherein plurality of processing cores comprises at least three processing cores.

16. The method of claim 15, further comprising:

generating an interrupt request, by the first core, to each of the other of the plurality of processing cores, in response to said encountering the architectural instruction; and

wherein said updating is performed in response to receiving the interrupt request.

17. The method of claim 16, further comprising:

disabling, by the first core, interrupts in response to said encountering the architectural instruction until after all of the plurality of processing cores have updated the respective architecturally-visible storage resource with the value; and

disabling, by each of the other of the plurality of processing cores, interrupts in response to receiving the interrupt request from the first core until after all of the plurality of processing cores have updated the respective architecturally-visible storage resource with the value.

18. The method of claim 15, wherein the microprocessor further includes a hardware semaphore shared by the plurality of processing cores, the method further comprising:

obtaining, by the first core, ownership of the hardware semaphore, prior to said providing the value to each of the other of the plurality of processing cores.

19. The method of claim 15, wherein said providing the value is performed by microcode of the first core, and wherein said updating is performed by microcode of each of the plurality of processing cores.

20. The method of claim 15, wherein the microprocessor further includes a memory shared by the plurality of processing cores, wherein said providing the value comprises:

writing, by the first core, the value to the shared memory.

21. The method of claim 15, wherein the microprocessor further includes an uncore control unit shared by the plurality of processing cores, the method further comprising:

making, by each core of the plurality of processing cores, a synchronization request to the uncore control unit prior to said updating the respective architecturally-visible storage resource of the core with the value.

22. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said non-transitory computer usable medium for specifying a microprocessor with a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource;

wherein a first core of the plurality of processing cores is configured to;

encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction; and

in response to encountering the architectural instruction;

communicate an update message to all of the other of the plurality of processing cores;

provide the value to all of the other of the plurality of processing cores; and

update the respective architecturally-visible storage resource of the first core with the value;

wherein each core of all the other of the plurality of processing cores than the first core is configured to respond to the update message by updating the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction; and

wherein plurality of processing cores comprises at least three processing cores.