Memory device that communicates error correction results to a host

• US 9,891,987 B2
• Filed: 03/04/2016
• Issued: 02/13/2018
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kodera, Shunsuke, Kitazume, Toshihiko, Kada, Kenichirou, Tsuji, Nobuhiro, Takeda, Shinya, Iwata, Tetsuya, Furuyama, Yoshio, Narai, Hirosuke
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US15/061,977
• Publication Number:
  US 20170060676A1
• Time in Patent Office: 711 Days
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.

Claims

1. A memory device, comprising:

a semiconductor memory unit;

a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, the page being divided into unit regions; and

an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page for up to a maximum number of error bits for each unit region of the page and to detect a total number of error bits in the data read for each unit region of the page, wherein

the controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not the total number of error bits detected in the data read from each unit region of the page by the ECC circuit is greater than a predetermined value that is less than the maximum number of error bits per unit region.

2. The memory device according to claim 1, wherein

the controller is further configured to determine whether or not the total number of error bits detected by the ECC circuit in the data read from each unit region of the page is greater than the predetermined value.

3. The memory device according to claim 1, wherein

the controller includes a storage region in which operational settings of the memory device are stored, the operational settings including a first entry indicating the predetermined value and a second entry that stores the information.

4. The memory device according to claim 3, wherein

the predetermined value in the first entry is settable through a command received from the host through the serial interface.

5. The memory device according to claim 3, wherein

the controller transmits the information to the host in response to a command to read the second entry, which is received through the serial interface.

6. The memory device according to claim 1, wherein

the unit region corresponds to a sector.

7. The memory device according to claim 1, wherein

the serial interface conforms to Serial Peripheral Interface (SPI).

8. The memory device according to claim 1, further comprising:

a first pin through which a chip select signal can be received;

a second pin through which a clock signal can be received; and

a third pin through which a command can be received in synchronization with the clock signal, wherein

the controller recognizes a signal received by the third pin immediately after the chip select signal is asserted as a command.

9. A memory device, comprising:

a semiconductor memory unit;

a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, the page being divide into unit regions; and

an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page and detect a number of error bits in data read from each unit region of the page, wherein

the controller is further configured to transmit, through the serial interface to the host, the number of error bits detected by the ECC circuit in the data read from each unit region of the page.

10. The memory device according to claim 9, wherein

the number of error bits detected by the ECC circuit in the data read from each unit region of the page is stored in the memory device, and

the controller transmits the number to the host, in response to a command to read the number, which is received through the serial interface.

11. The memory device according to claim 9, wherein

the unit region corresponds to a sector.

12. The memory device according to claim 9, wherein

the serial interface conforms to Serial Peripheral Interface (SPI).

13. The memory device according to claim 9, further comprising:

a first pin through which a chip select signal can be received;

a second pin through which a clock signal can be received; and

a third pin through which a command can be received in synchronization with the clock signal, wherein

the controller recognizes a signal received by the third pin immediately after the chip select signal is asserted as a command.

14. A method of informing a host whether or not a refresh process should be carried out in a memory device having a semiconductor memory unit and a controller configured to communicate with the host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, said method comprising:

performing a read operation on a page in the semiconductor memory unit;

performing error correction with respect to data read from each unit region of the page; and

transmit through the serial interface to the host, information that indicates whether or not a number of error bits detected in the data read from each unit region of the page through the error correction is greater than a predetermined value.

15. The method according to claim 14, further comprising:

determining whether or not a number of error bits detected in the data read from each unit region of the page through the error correction is greater than a predetermined value; and

setting the information in accordance with the determination.

16. The method according to claim 14, wherein

the controller includes a storage region in which operational settings of the memory device are stored, the operational settings including a first entry indicating the predetermined value and a second entry that stores the information.

17. The method according to claim 16, further comprising:

setting the predetermined value in the first entry in response to a command received from the host through the serial interface.

18. The method according to claim 16, wherein

the information is transmitted to the host, in response to a command to read the second entry, which is received through the serial interface.

19. The method according to claim 14, wherein

the unit region corresponds to a sector.

20. The method according to claim 14, wherein

the memory device further includes a first pin configured to receive through which a chip select signal is received, a second pin through which a clock signal is received, and a third pin through which a command is received in synchronization with the clock signal, and

the controller recognizes a signal received by the third pin immediately after the chip select signal is asserted as a command.