Management of memory units

• US 9,892,033 B1
• Filed: 06/24/2014
• Issued: 02/13/2018
• Est. Priority Date: 06/24/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Sabbag, Erez
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Wong, Nanci
• Application Number:
  US14/313,821
• Time in Patent Office: 1,330 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A method for memory management, the method may include calculating, by a memory controller, an estimate of an effect of read operations on a first flash memory entity; and performing, by the memory controller, at least one memory management operation in response to the estimate of the effect of read operations on the first flash memory entity.

Claims

1. A method for memory management, the method comprising:

maintaining, by a memory controller, read counters for each flash memory entity in a flash memory array coupled to the memory controller, the read counters being configured to store indications about effects of read operations on associated flash memory entities and being configured to be incremented each time associated flash memory entities are subjected to a read operation;

calculating, with reference to a first read counter associated with a first flash memory entity, an estimate of an effect of read operations on the first flash memory entity; and

performing, by the memory controller, at least one memory management operation in response to the estimate of the effect of read operations on the first flash memory entity, wherein the at least one memory management operation is performed with reference to a programming parameter that is chosen based on a read disturb scenario and which indicates whether the at least one memory management operation is to move a data unit from the first flash memory entity to another flash memory entity having a same or lower density level, wherein the calculating of the estimate of the effect of read operations is responsive to a relationship between (a) a bit error rate of data stored in a group of flash memory cells that belongs to the first flash memory entity and (b) a number of program erase cycles that the group of flash memory cells has undergone.

2. The method according to claim 1 wherein the first flash memory entity stores the data unit at a first density level;

wherein the performing of the at least one memory management operation comprises writing the data unit to a second flash memory entity at a second density level when the estimate of the effect of read operations on the first flash memory entity exceeds a read disturb threshold; and

wherein the second density level that is lower than the first density level.

3. The method according to claim 2 comprising receiving requests to read the data unit and reading the data unit from the second flash memory entity and wherein the second flash memory entity is configured to store data units at the first density level even though the second flash memory entity is used to store the data unit at the second density level.

4. The method according to claim 2 wherein the method comprises erasing the first flash memory entity after writing the data unit to the second flash memory entity.

5. The method according to claim 2 wherein the method comprises:

preventing from erasing the first flash memory entity after writing the data unit to the second flash memory entity;

determining to stop using the second flash memory entity for storing the data; and

utilizing the first memory entity for reading the data.

6. The method according to claim 1, wherein the calculating of the estimate of the effect of read operations is responsive to a number of read operations of a group of flash memory cells that belongs to the first flash memory entity.

7. The method according to claim 1 wherein the first flash memory entity is in an erased state during the calculating of the estimate and wherein the at least one memory management operation comprises determining when to allocate the first flash memory entity for storing data.

8. The method according to claim 1 wherein the method comprises:

calculating, by the memory controller, estimates of effects of read operations on multiple flash memory entities;

wherein the multiple flash memory entities comprise the first flash memory entity; and

performing, by the memory controller, at least one memory management operation in response to the estimates of the effects of read operations on the multiple flash memory entities.

9. The method according to claim 8 wherein the at least one memory management operation comprises wear leveling.

10. A non-transitory computer readable medium that stores instructions that once executed by the computer cause the computer to execute the stages of:

maintaining read counters for each flash memory entity in a flash memory array, the read counters being configured to store indications about effects of read operations on associated flash memory entities and being configured to be incremented each time associated flash memory entities are subjected to a read operation;

calculating, with reference to a first read counter associated with a first flash memory entity, an estimate of an effect of read operations on the first flash memory entity; and

performing at least one memory management operation in response to the estimate of the effect of read operations on the first flash memory entity, wherein the at least one memory management operation is performed with reference to a programming parameter that is chosen based on a read disturb scenario and which indicates whether the at least one memory management operation is to move a data unit from the first flash memory entity to another flash memory entity having a same or lower density level, wherein the calculating of the estimate of the effect of read operations is responsive to a relationship between (a) a bit error rate of data stored in a group of flash memory cells that belongs to the first flash memory entity and (b) a number of program erase cycles that the group of flash memory cells has undergone.

11. The non-transitory computer readable medium according to claim 10 wherein the first flash memory entity stores the data unit at a first density level;

wherein the performing of the at least one memory management operation comprises writing the data unit to a second flash memory entity at a second density level when the estimate of the effect of read operations on the first flash memory entity exceeds a read disturb threshold; and

wherein the second density level that is lower than the first density level.

12. The non-transitory computer readable medium according to claim 11 that stores instructions for receiving requests to read the data unit and reading the data unit from the second flash memory entity.

13. The non-transitory computer readable medium according to claim 11 wherein the non-transitory computer readable medium stores instructions for erasing the first flash memory entity after writing the data unit to the second flash memory entity.

14. The non-transitory computer readable medium according to claim 11 wherein the non-transitory computer readable medium stores instructions for:

preventing from erasing the first flash memory entity after writing the data unit to the second flash memory entity;

determining to stop using the second flash memory entity for storing the data; and

utilizing the first memory entity for reading the data.

15. The non-transitory computer readable medium according to claim 10, wherein the calculating of the estimate of the effect of read operations is responsive to a number of read operations of a group of flash memory cells that belongs to the first flash memory entity.

16. The non-transitory computer readable medium according to claim 10 wherein the first flash memory entity is in an erased state during the calculating of the estimate and wherein the at least one memory management operation stores instructions for determining when to allocate the first flash memory entity for storing data.

17. The non-transitory computer readable medium according to claim 10 wherein the non-transitory computer readable medium stores instructions for:

calculating, by the memory controller, estimates of effects of read operations on multiple flash memory entities;

wherein the multiple flash memory entities comprise the first flash memory entity; and

performing, by the memory controller, at least one memory management operation in response to the estimates of the effects of read operations on the multiple flash memory entities.

18. A memory controller that comprises a read circuit, a write circuit, a read effect estimating circuit, and a memory management circuit;

wherein the read circuit is arranged to assist in reading data from a first flash memory entity;

wherein the write circuit is arranged to assist in writing data to the first flash memory entity;

wherein the read effect estimating circuit is arranged to maintain read counters for each flash memory entity in a flash memory array, the read counters being configured to store indications about effects of read operations on associated flash memory entities and being configured to be incremented each time associated flash memory entities are subjected to a read operation;

calculate, with reference to a first read counter associated with the first flash memory entity, an estimate of an effect of read operations on the first flash memory entity;

wherein the memory management circuit is arranged to perform at least one memory management operation in response to the estimate of the effect of read operations on the first flash memory entity; and

wherein the at least one memory management operation is performed with reference to a programming parameter that is chosen based on a read disturb scenario and which indicates whether the at least one memory management operation is to move a data unit from the first flash memory entity to another flash memory entity having a same or lower density level, wherein the read effect estimating circuit is arranged to calculate the estimate of the effect of read operations on the first flash memory entity in response to a relationship between (a) a bit error rate of data stored in a group of flash memory cells that belongs to the first flash memory entity and (b) a number of program erase cycles that the group of flash memory cells has undergone.

19. The memory controller according to claim 18 wherein the first flash memory entity is arranged to store the data unit at a first density level;

and wherein the memory management circuit is arranged to perform the at least one memory management operation by instructing the write circuit to write the data unit to a second flash memory entity at a second density level when the estimate of the effect of read operations on the first flash memory entity exceeds a read disturb threshold; and

wherein the second density level that is lower than the first density level.

20. The memory controller according to claim 19 wherein the memory controller is arranged to prevent from erasing the first flash memory entity after writing the data unit to the second flash memory entity;

determine to stop using the second flash memory entity for storing the data; and

utilize the first memory entity for reading the data.

21. The memory controller according to claim 18 wherein the read effect estimating circuit is arranged to calculate the estimate of the effect of read operations on the first flash memory entity in response to a number of read operations of a group of flash memory cells that belongs to the first flash memory entity.