Decryption of encrypted instructions using keys selected on basis of instruction fetch address

• US 9,892,283 B2
• Filed: 10/15/2015
• Issued: 02/13/2018
• Est. Priority Date: 05/25/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Bean, Brent, Crispin, Thomas A.
• Primary Examiner(s): Rashid, Harunur
• Application Number:
  US14/884,502
• Publication Number:
  US 20160104009A1
• Time in Patent Office: 852 Days
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2212/402 Encrypted data
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/20 Manipulating the length of blocks of bits, e.g. padding or block truncation
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0891 Revocation or update of secret information, e.g. encryption key update or rekeying
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

Claims

1. A microprocessor for executing encrypted instructions and non encrypted (plain text) instructions comprising:

an instruction cache for storing both the encrypted instructions and the non encrypted instructions;

fetch logic configured to fetch both the encrypted instructions and the non encrypted instructions from the instruction cache, the fetch logic further comprising;

a key expander;

a secure memory configured to store a plurality of master keys;

key selection logic configured to select a set of one or more master keys from the secure memory based upon an instruction fetch address for an encrypted instruction, wherein the selected master keys are used by the key expander, along with the instruction fetch address, to decrypt the encrypted instructions fetched from the instruction cache;

decryption logic configured to use the selected set of one or more master keys, or a decryption key provided by the key expander derived from the selected set of one or more master keys, to decrypt the encrypted instructions fetched from the instruction cache; and

decryption key generation logic configured to derive a decryption key from the selected set of one or more master keys;

wherein the encrypted instructions are grouped into blocks of instructions having a length not greater than the decryption key'"'"'s length, and the decryption key generation logic is configured to derive a new decryption key for each block of instructions based upon a fetch address of an encrypted instruction in the block of instructions; and

wherein the microprocessor executes the decrypted instructions.

2. The microprocessor of claim 1, wherein the decryption key generation logic is configured to derive a new decryption key with each fetch quantum.

3. The microprocessor of claim 2, wherein each decryption key has a byte length of t=2^s, where s is the number of bytes of a fetch quantum.

4. The microprocessor of claim 1, wherein the decryption key generation logic is configured to derive a new decryption key by rotating one of the selected set of one or more master keys by an amount based upon the encrypted instruction fetch address.

5. The microprocessor of claim 4, wherein a [b:

0] subset of the encrypted instruction fetch address does not affect the amount by which the master key is rotated, wherein 0 and b represent the least significant bit and the b^th least significant bit, respectively, of the encrypted instruction fetch address.

6. The microprocessor of claim 4, wherein a [d:

c] subset of the fetch address determines an extent to which the master key is rotated, wherein c and d represent the c^th least significant bit and the d^th least significant bit, respectively, of the encrypted instruction fetch address.

7. The microprocessor of claim 6, wherein the decryption key generation logic is configured to rotate the master key by one of n possible rotation amounts, where n=2^m, where m is a number of bits in the [d:

c] subset of the encrypted instruction fetch address.

8. The microprocessor of claim 7, wherein the decryption key generation logic is configured to derive a new decryption key by selecting a new set of one or more master keys based upon a new encrypted instruction fetch address.

9. The microprocessor of claim 8, wherein a [f:

e] subset of the new encrypted instruction fetch address determines a makeup of the new set of one or more master keys, wherein e and f represent the e^th least significant bit and the f^th least significant bit, respectively, of the encrypted instruction fetch address.

10. The microprocessor of claim 9, wherein the decryption key logic is configured to select any one of q available sets of one or more master keys, where p=2^q, where q is a number of possible values in the [f:

e] subset of the new encrypted instruction fetch address.

11. A method of securely executing encrypted instructions within a microprocessor, the method comprising:

providing an instruction cache for storing both the encrypted instructions and non encrypted instructions;

storing a plurality of master keys in a secure memory;

fetching encrypted instructions from the instruction cache, the fetching utilizing fetch logic having a key expander;

selecting a set of one or more master keys from the secure memory based upon an instruction fetch address for an encrypted instruction;

decrypting the encrypted instruction fetched from the instruction cache using the selected set of one or more master keys or a decryption key derived by the key expander from the selected set of one or more master keys to decrypt the encrypted instructions fetched from the instruction cache wherein the encrypted instructions are grouped into blocks of instructions having a length not greater than the decryption key'"'"'s length;

deriving a new decryption key from the selected set of one or more master keys based upon an encrypted instruction fetch address for each block of instructions; and

securely executing the decrypted instructions within the microprocessor.

12. The method of claim 11, further comprising deriving a new decryption key based upon an encrypted instruction fetch address with each fetch quantum.

13. The method of claim 12, wherein each decryption key has a byte length of t=2^s, where s is the number of bytes of a fetch quantum.

14. The method of claim 11, further comprising deriving a new decryption key by rotating one of the selected one or more master keys based upon the encrypted instruction fetch address.

15. The method of claim 14, wherein a [b:

0] subset of the encrypted instruction fetch address does not affect the amount by which the master key is rotated, wherein 0 and b represent the least significant bit and the b^th least significant bit, respectively, of the encrypted instruction fetch address.

16. The method of claim 14, wherein the action of rotating comprises rotating the master key by an amount determined by a value represented by a [d:

c] subset of the fetch address, wherein c and d represent the c^th least significant bit and the d^th least significant bit, respectively, of the encrypted instruction fetch address.

17. The method of claim 16, wherein the action of rotating rotates the master key by one of n possible rotation amounts, where n=2^m, where m is a number of bits in the [d:

c] subset of the encrypted instruction fetch address.

18. The method of claim 11, further comprising deriving a new decryption key by selecting a new set of one or more master keys based upon a new encrypted instruction fetch address.

19. The method of claim 18, wherein the action of selecting a new set of one or more master keys is determined by a value represented by a [f:

e] subset of the new encrypted instruction fetch address, wherein e and f represent the e^th least significant bit and the f^th least significant bit, respectively, of the encrypted instruction fetch address.

20. The method of claim 19, wherein the action of selecting a new set of one or more master keys comprises selecting any one of q available sets of one or more master keys, where p=2^q, where q is a number of possible values in the [f:

e] subset of the new encrypted instruction fetch address.