Half density ferroelectric memory and operation

• US 9,892,776 B2
• Filed: 06/13/2016
• Issued: 02/13/2018
• Est. Priority Date: 06/13/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Ingalls, Charles L.
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/181,188
• Publication Number:
  US 20170358338A1
• Time in Patent Office: 610 Days
• Field of Search: 365145, 3652101, 3651852, 36523003, 365 63
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

Claims

1. A method of operating a ferroelectric memory array, comprising:

receiving an indication to operate a plurality of memory cells of the ferroelectric memory array in a half density mode;

identifying a first half of the plurality of memory cells as active memory cells;

identifying a second half of the plurality of memory cells as reference memory cells;

pairing each active memory cell of the first half to a reference memory cell of the second half;

activating a first common access line in electronic communication with the first half and the second half of the plurality of memory cells, wherein the plurality of memory cells comprises a first subset of the ferroelectric memory array and a remainder of the memory cells comprises a second subset of the ferroelectric memory array;

operating the first subset of the ferroelectric memory array in the half density mode; and

operating the second subset of the ferroelectric memory array in a normal mode, wherein each memory cell coupled to a second common access line of the second subset is an active memory cell.

2. The method of claim 1, further comprising:

deactivating a plurality of sense components in electronic communication with the reference memory cells.

3. The method of claim 1, further comprising:

determining a logic state for the active memory cell of the plurality of memory cells; and

writing to the reference memory cell paired to the active memory cell a logic state opposite the logic state of the active memory cell.

4. The method of claim 1, further comprising:

storing a logic state of at least one reference memory of the first subset of the ferroelectric memory array in the active memory cell of the second subset of the ferroelectric memory array.

5. The method of claim 1, wherein the first subset of the ferroelectric memory array comprises at least one of a sector or a bank.

6. The method of claim 1, wherein receiving the indication comprises:

receiving the indication from a user or device of which the ferroelectric memory array is a component.

7. The method of claim 1, further comprising:

determining that a temperature of the ferroelectric memory array is outside a range of temperatures, wherein receiving the indication to operate the plurality of memory cells in the half density mode is based at least in part on the determination.

8. The method of claim 1, wherein the active memory cell and the reference memory cell of each pair are in electronic communication with the common access line.

9. An electronic memory apparatus, comprising:

a sense component in electronic communication with a first ferroelectric memory cell and a second ferroelectric memory cell;

a switch between the second ferroelectric memory cell and the sense component; and

a controller in electronic communication with the sense component, the first and second ferroelectric memory cells, and the switch, wherein the controller is operable to;

receive an access operation request for the first ferroelectric memory cell;

activate a first common access line in electronic communication with the first ferroelectric memory cell and the second ferroelectric memory cell;

select the first ferroelectric memory cell and the second ferroelectric memory cell based at least in part on activating the first common access line

activate the switch between the second ferroelectric memory cell and the sense component based at least in part on receiving the access operation request for the first ferroelectric memory cell;

activate the sense component, wherein the second ferroelectric memory cell comprises a reference input to the sense component, wherein a plurality of ferroelectric memory cells comprises a first subset of a ferroelectric memory array and a remainder of the plurality of ferroelectric memory cells comprises a second subset of the ferroelectric memory array;

operate the first subset of the ferroelectric memory array in a half density mode; and

operate the second subset of the ferroelectric memory array in a normal mode, wherein each ferroelectric memory cell coupled to a second common access line of the second subset is an active ferroelectric memory cell.

10. The electronic memory apparatus of claim 9, further comprising:

an isolation device between the first ferroelectric memory cell and the sense component,

wherein the controller is operable to;

activate the isolation device based at least in part on receiving the access operation request for the first ferroelectric memory cell.

11. The electronic memory apparatus of claim 9, wherein the controller is operable to:

determine a logic state of the first ferroelectric memory cell based at least in part on activating the sense component;

write the logic state of the first ferroelectric memory cell back to the first ferroelectric memory cell; and

write a logic state to the second ferroelectric memory cell that is opposite the logic state of the first ferroelectric memory cell.