Systems and methods for programming data to storage devices

• US 9,892,793 B1
• Filed: 07/25/2016
• Issued: 02/13/2018
• Est. Priority Date: 07/25/2016
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Bandic, Zvonimir, Qin, Minghai, Song, Seung-Hwan, Sun, Chao
• Primary Examiner(s): HOANG, TRI M
• Application Number:
  US15/219,220
• Publication Number:
  US 20180025782A1
• Time in Patent Office: 568 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits.

Claims

1. A method comprising:

receiving one or more first write commands to write a first set of data to a storage device;

programming the first set of data in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells, wherein each of the plurality of memory cells is programmed with two bits of data from the first set of data;

receiving one or more second write commands to write a second set of data to the storage device; and

programming the second set of data in the plurality of memory cells programmed with the first set of data, wherein the second set of data is programmed using a second plurality of program levels available in the plurality of memory cells, each of the second plurality of program levels is different from each of the first plurality of program levels, and each of the plurality of memory cells is programmed with two bits of data from the second set of data,

wherein each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits,

wherein first and second bit pairs of the bit patterns mapped to the first plurality of program levels are unique across the first plurality of program levels, and

wherein first and second bit pairs of the bit patterns mapped to the second plurality of program levels are unique across the second plurality of program levels.

2. The method of claim 1, further comprising:

setting a flag upon programming the plurality of memory cells using the first plurality of program levels; and

clearing the flag upon programming the plurality of memory cells using the second plurality of program levels.

3. The method of claim 1, wherein threshold voltages associated with the first plurality of program levels are less than threshold voltages associated with the second plurality of program levels.

4. The method of claim 1, wherein the first bit of the first and second bit pairs corresponds to a first logical page of data and the second bit of the first and second bit pairs corresponds to a second logical page of data.

5. The method of claim 1, wherein a third bit of the bit patterns mapped to the first plurality of program levels is uniform across the first plurality of program levels, and

wherein the third bit of the bit patterns mapped to the second plurality of program levels is uniform across the second plurality of program levels.

6. The method of claim 5, wherein the third bit corresponds to a third logical page unused for storing data.

7. The method of claim 1, wherein the storage device is a 3D NAND flash memory device.

8. A data storage system, comprising:

a plurality of storage devices, each storage device comprising a plurality of multi-level cells; and

a controller coupled to the plurality of storage devices, wherein the controller is configured to;

receive one or more first write commands to write a first set of data to the plurality of storage devices;

program the first set of data in the plurality of storage devices using a first plurality of program levels available in the plurality of storage devices, wherein two bits of data from the first set of data are programmed in each multi-level cell programmed in the plurality of storage devices;

receive a second write command to write a second set of data to the plurality of storage devices; and

program the second set of data in the plurality of storage devices programmed with the first set of data, wherein the second set of data is programmed using a second plurality of program levels available in the plurality of storage devices, each of the plurality of program levels is different from each of the first plurality of program levels and two bits of data from the second set of data are programmed in each of the multi-level cell programmed in the plurality of storage devices,

wherein each program level of the first and second pluralities of program levels is mapped to a bit pattern comprising three bits,

wherein first and second bit pairs of the bit patterns mapped to the first plurality of program levels are unique across the first plurality of program levels, and

wherein first and second bit pairs of the bit patterns mapped to the second plurality of program levels are unique across the second plurality of program levels.

9. The data storage system of claim 8, wherein the controller is further configured to:

set a flag upon programming the plurality of storage devices using the first plurality of program levels; and

clear the flag upon programming the plurality of storage devices using the second plurality of program levels.

10. The data storage system of claim 8, wherein threshold voltages associated with the first plurality of program levels are less than threshold voltages associated with the second plurality of program levels.

11. The data storage system of claim 8, wherein the first bit of the first and second bit pairs corresponds to a first logical page of data and the second bit of the first and second bit pairs corresponds to a second logical page of data.

12. The data storage system of claim 8, wherein a third bit of the bit patterns mapped to the first plurality of program levels is uniform across the first plurality of program levels, and

wherein the third bit of the bit patterns mapped to the second plurality of program levels is uniform across the second plurality of program levels.

13. The data storage system of claim 12, wherein the third bit corresponds to a third logic page unused for storing data.

14. The data storage system of claim 8, wherein the storage device is a flash memory device, the flash memory device has a 3D NAND flash memory structure.

15. A machine-readable media encoded with executable instructions which, when executed by a processor, cause the processor to perform operations comprising:

receiving one or more first write commands to write a first set of data to a storage device;

programming the first set of data in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells, wherein each of the plurality of memory cells is programmed with two bits of data from the first set of data;

setting a flag upon programming the plurality of memory cells using the first plurality of program levels;

receiving a second write command to write a second set of data to the storage device;

programming the second set of data in the plurality of memory cells programmed with the first set of data, wherein the second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels and each of the plurality of memory cells is programmed with two bits of data from the second set of data; and

clearing the flag upon programming the plurality of memory cells using the second plurality of program levels,

wherein each program level of the first and second pluralities of program levels is mapped to a bit pattern comprising three bits,

wherein first and second bit pairs of the bit patterns mapped to the first plurality of program levels are unique across the first plurality of program levels,

wherein first and second bit pairs of the bit patterns mapped to the second plurality of program levels are unique across the second plurality of program levels.

16. The machine-readable media of claim 15, wherein threshold voltages associated with the first plurality of program levels are less than threshold voltages associated with the second plurality of program levels.

17. The machine-readable media of claim 15, wherein the first bit of the first and second bit pairs corresponds to a first logical page of data and the second bit of the first and second bit pairs corresponds to a second logical page of data.

18. The machine-readable media of claim 15, wherein a third bit of the bit patterns mapped to the first plurality of program levels is uniform across the first plurality of program levels,

wherein the third bit of the bit patterns mapped to the second plurality of program levels are uniform across the second plurality of program levels, and

wherein the third bit corresponds to a third logical page unused for storing data.

19. The machine-readable media of claim 15, wherein the storage device is a flash memory device, the flash memory device has a 3D NAND flash memory structure.