Method and apparatus with program suspend using test mode

• US 9,892,794 B2
• Filed: 01/02/2017
• Issued: 02/13/2018
• Est. Priority Date: 01/04/2016
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: Ip Gem Group, LLC
• Inventors: Micheloni, Rino, Aldarese, Antonio, Scommegna, Salvatrice
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/396,721
• Publication Number:
  US 20170194053A1
• Time in Patent Office: 407 Days
• Field of Search: 36518517, 36518529, 36518518, 36518519, 36518522, 36523006
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.

Claims

1. A method comprising:

initiating operation of a nonvolatile memory device that is not capable of performing a program suspend command;

sending a first program instruction and a first set of trim values from a nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in trim registers of the nonvolatile memory device;

exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of a NAND memory array of the nonvolatile memory device;

after performing the first program slice, sending a second program instruction and a second set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers;

exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and

if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, performing the one or more pending read command prior to performing the second program slice.

2. The method of claim 1 wherein the first set of trim values include one or more value that indicates the first predetermined number of program pulses and further wherein the second set of trim values include one or more value that indicates the second predetermined number of program pulses.

3. The method of claim 1 wherein the second set of trim values include one or more value that indicates a programming step such that the last voltage step of the first slice is repeated.

4. The method of claim 1 further comprising:

when one or more read command is pending at the nonvolatile memory controller when the first program slice is completed;

performing a quality of service analysis;

performing the one or more pending read command prior to performing the second program slice when the quality of service analysis indicates that a program suspend is required to meet a quality of service criteria; and

not performing the one or more pending read command prior to performing the second program slice when the quality of service analysis does not indicate that a program suspend is required to meet the quality of service criteria.

5. The method of claim 1 further comprising

sending a third program instruction and a third set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the third program instruction and the third set of trim values are stored in trim registers of the nonvolatile memory device;

exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a third program slice by executing the third program instruction using the third set of trim values so as to apply a third predetermined number of program pulses to the memory cells of the NAND memory array; and

when one or more additional read command is pending at the nonvolatile memory controller when the second program slice is completed, performing the one or more additional pending read command prior to performing the third program slice.

6. The method of claim 5 further comprising:

when the one or more pending read command is performed prior to performing the second program slice, determining a suspend time;

determining whether a limit has been reached using the determined suspend time; and

when the limit has been reached, not performing the one or more additional pending read command prior to performing the third program slice.

7. A nonvolatile memory controller comprising:

a NAND shared algorithm circuit configured to;

send a first program instruction and a first set of trim values to a nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in trim registers of the nonvolatile memory device, wherein the nonvolatile memory device is not capable of performing a program suspend command;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of a NAND memory array of the nonvolatile memory device;

after performing the first program slice, send a second program instruction and a second set of trim values to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and

if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, perform the one or more pending read command prior to sending the second program instruction and the second set of trim values from the nonvolatile memory controller to the nonvolatile memory device.

8. The nonvolatile memory controller of claim 7 wherein the first set of trim values include one or more value that indicates the first predetermined number of program pulses and further wherein the second set of trim values include one or more value that indicates the second predetermined number of program pulses.

9. The nonvolatile memory controller of claim 8 wherein the second set of trim values include one or more value that indicates a programming step such that the last voltage step of the first slice is repeated during the second slice.

10. The nonvolatile memory controller of claim 8

wherein, when the one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, the NAND shared algorithm circuit is further configured to:

perform a quality of service analysis;

perform the one or more pending read command if the quality of service analysis indicates that a program suspend is required to meet a quality of service criteria; and

not perform the one or more pending read command if the quality of service analysis indicates that a program suspend is not required to meet the quality of service criteria.

11. The nonvolatile memory controller of claim 7 wherein the NAND shared algorithm circuit is further configured to:

send a third program instruction and a third set of trim values to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the third program instruction and the third set of trim values are stored in trim registers of the nonvolatile memory device;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a third program slice by executing the third program instruction using the third set of trim values so as to apply a third predetermined number of program pulses to the memory cells of the NAND memory array; and

if one or more additional read command is pending when the second program slice is completed, perform the one or more additional pending read command prior to sending the third program instruction and the third set of trim values from the nonvolatile memory controller to the nonvolatile memory device.

12. The nonvolatile memory controller of claim 11

wherein, when the one or more pending read command is performed prior to sending the second program instruction and the second set of trim values, the NAND shared algorithm circuit is configured to:

determine a suspend time;

determine whether a limit has been reached using the determined suspend time; and

when the limit has been reached, not performing the one or more additional pending read command prior to sending the third program instruction and the third set of trim values.

13. A nonvolatile memory system comprising:

a nonvolatile memory device including trim registers, a microcontroller and a NAND memory array, the microcontroller coupled to the trim registers and to the NAND memory array;

a nonvolatile memory controller configured to;

send a first program instruction and a first set of trim values to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in the trim registers of the nonvolatile memory device;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of the NAND memory array;

after performing the first program slice, send a second program instruction and a second set of trim values to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and

if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, perform the one or more pending read command prior to sending the second program instruction and the second set of trim values to the nonvolatile memory device.

14. The nonvolatile memory system of claim 13 wherein, when the one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, the nonvolatile memory controller is further configured to:

perform a quality of service analysis;

perform the one or more pending read command if the quality of service analysis indicates that a program suspend is required to meet a quality of service criteria; and

not perform the one or more pending read command if the quality of service analysis indicates that a program suspend is not required to meet the quality of service criteria.

15. The nonvolatile memory system of claim 13 wherein the nonvolatile memory device is configured to:

send a third program instruction and a third set of trim values to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the third program instruction and the third set of trim values are stored in trim registers of the nonvolatile memory device;

communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a third program slice by executing the third program instruction using the third set of trim values so as to apply a third predetermined number of program pulses to the memory cells of the NAND memory array; and

if one or more additional read command is pending when the second program slice is completed, perform the one or more additional pending read command prior to sending the third program instruction and the third set of trim values to the nonvolatile memory device.

16. The nonvolatile memory system of claim 13 wherein, when the one or more pending read command is performed prior to sending the second program instruction and the second set of trim values to the nonvolatile memory device, the NAND shared algorithm circuit is configured to:

determine a suspend time;

determine whether a limit has been reached using the determined suspend time; and

when the limit has been reached, not performing the one or more pending read command prior to sending the third program instruction and the third set of trim values to the nonvolatile memory device.

17. A method comprising:

initiating operation of a nonvolatile memory device that is not capable of performing a program suspend command;

sending a first program instruction and a first set of trim values from a nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in the trim registers of the nonvolatile memory device;

exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to execute the first program instruction using the first set of trim values so as to perform a first program operation on memory cells of a NAND memory array of the nonvolatile memory device;

when one or more read command for reading the nonvolatile memory device is pending at the nonvolatile memory controller at the end of the first program operation, sending an abort instruction from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the abort instruction is stored in the trim registers of the nonvolatile memory device;

in response to the abort instruction, aborting the first program operation;

determining a program time, wherein the determined program time corresponds to the time during which the first program operation was performed on the memory cells of the NAND memory array;

after the aborting, communicating with the nonvolatile memory device such that the nonvolatile memory device performs one or more read operation corresponding to the one or more pending read command;

sending a second program instruction and a second set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers of the nonvolatile memory device; and

exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to execute the second program instruction using the second set of trim values so as to perform a second program operation on the memory cells of the NAND memory array, the second program operation beginning at a programming step corresponding to the determined program time.

18. The method of claim 17 wherein the second program operation begins at a programming step that is a repeat of a last programming step of the first program operation.

19. The method of claim 17 wherein communicating with the nonvolatile memory device such that the nonvolatile memory device performs one or more read operation corresponding to the one or more pending read command further comprises:

sending a read instruction and a third set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the read instruction and the third set of trim values are stored in the trim registers of the nonvolatile memory device; and

executing the read instruction at the nonvolatile memory device using the third set of trim values so as to perform the read operation.

20. The method of claim 17 wherein the program time is determined by monitoring a read/busy signal of the nonvolatile memory device.