Method and apparatus with program suspend using test mode
First Claim
1. A method comprising:
- initiating operation of a nonvolatile memory device that is not capable of performing a program suspend command;
sending a first program instruction and a first set of trim values from a nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in trim registers of the nonvolatile memory device;
exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of a NAND memory array of the nonvolatile memory device;
after performing the first program slice, sending a second program instruction and a second set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers;
exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and
if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, performing the one or more pending read command prior to performing the second program slice.
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Accused Products
Abstract
A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.
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Citations
20 Claims
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1. A method comprising:
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initiating operation of a nonvolatile memory device that is not capable of performing a program suspend command; sending a first program instruction and a first set of trim values from a nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in trim registers of the nonvolatile memory device; exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of a NAND memory array of the nonvolatile memory device; after performing the first program slice, sending a second program instruction and a second set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers; exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, performing the one or more pending read command prior to performing the second program slice. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A nonvolatile memory controller comprising:
a NAND shared algorithm circuit configured to; send a first program instruction and a first set of trim values to a nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in trim registers of the nonvolatile memory device, wherein the nonvolatile memory device is not capable of performing a program suspend command; communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of a NAND memory array of the nonvolatile memory device; after performing the first program slice, send a second program instruction and a second set of trim values to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers; communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, perform the one or more pending read command prior to sending the second program instruction and the second set of trim values from the nonvolatile memory controller to the nonvolatile memory device. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A nonvolatile memory system comprising:
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a nonvolatile memory device including trim registers, a microcontroller and a NAND memory array, the microcontroller coupled to the trim registers and to the NAND memory array; a nonvolatile memory controller configured to; send a first program instruction and a first set of trim values to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in the trim registers of the nonvolatile memory device; communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a first program slice by executing the first program instruction using the first set of trim values so as to apply a first predetermined number of program pulses to memory cells of the NAND memory array; after performing the first program slice, send a second program instruction and a second set of trim values to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers; communicate with the nonvolatile memory device such that the nonvolatile memory device exits the test mode, the nonvolatile memory device operable upon exiting the test mode to perform a second program slice by executing the second program instruction using the second set of trim values so as to apply a second predetermined number of program pulses to the memory cells of the NAND memory array; and if one or more read command is pending at the nonvolatile memory controller when the first program slice is completed, perform the one or more pending read command prior to sending the second program instruction and the second set of trim values to the nonvolatile memory device. - View Dependent Claims (14, 15, 16)
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17. A method comprising:
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initiating operation of a nonvolatile memory device that is not capable of performing a program suspend command; sending a first program instruction and a first set of trim values from a nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in a test mode such that the first program instruction and the first set of trim values are stored in the trim registers of the nonvolatile memory device; exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to execute the first program instruction using the first set of trim values so as to perform a first program operation on memory cells of a NAND memory array of the nonvolatile memory device; when one or more read command for reading the nonvolatile memory device is pending at the nonvolatile memory controller at the end of the first program operation, sending an abort instruction from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the abort instruction is stored in the trim registers of the nonvolatile memory device; in response to the abort instruction, aborting the first program operation; determining a program time, wherein the determined program time corresponds to the time during which the first program operation was performed on the memory cells of the NAND memory array; after the aborting, communicating with the nonvolatile memory device such that the nonvolatile memory device performs one or more read operation corresponding to the one or more pending read command; sending a second program instruction and a second set of trim values from the nonvolatile memory controller to the nonvolatile memory device while the nonvolatile memory device is in the test mode such that the second program instruction and the second set of trim values are stored in the trim registers of the nonvolatile memory device; and exiting the test mode, the nonvolatile memory device operable upon exiting the test mode to execute the second program instruction using the second set of trim values so as to perform a second program operation on the memory cells of the NAND memory array, the second program operation beginning at a programming step corresponding to the determined program time. - View Dependent Claims (18, 19, 20)
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Specification