Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates

• US 9,892,800 B2
• Filed: 07/26/2016
• Issued: 02/13/2018
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LEBOEUF, JEROME LARRY
• Application Number:
  US15/220,375
• Publication Number:
  US 20170092370A1
• Time in Patent Office: 567 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H05K 999/99 dummy group
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface;

a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type;

a charge-trapping material; and

a plurality of conductors each extending lengthwise along a second direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the charge-trapping material, thereby forming in each active strip a NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent charge-trapping material and the conductors within the group, wherein the NOR string is associated with a pre-charge device on the active strip that pre-charges the second semiconductor layer to a voltage that is substantially held by virtue of a parasitic capacitance along the active strip during a program, program-inhibit, reading or erasing operation on the NOR string.

2. The memory structure of claim 1, further comprising

circuitry formed in and on the planar surface of the semiconductor substrate;

and

first and second sets of global conductive wiring each running along a direction that is parallel to the planar surface for connecting the conductors to the circuitry, wherein the first set of global wiring runs above the first and second stacks of active strips and the second set of global wiring runs underneath the first and second stacks of active strips.

3. The memory structure of claim 2, wherein the pre-charge device comprises at least one selected storage transistor and wherein the circuitry applies one of a plurality of configurations of voltages to cause the pre-charge device to pre-charge the parasitic capacitance of the second semiconductor layer to a selected one of several predetermined voltages, the selected predetermined voltage being selected for one of:

program, program-inhibit, reading and erasing data of the storage transistors.

4. The memory structure of claim 2, wherein the pre-charge device includes one or more pre-charge transistors having source and drain regions formed out of the second and the third semiconductor layers, respectively, wherein the circuitry applies one of a plurality of configurations of voltages to cause the pre-charge device to pre-charge the parasitic capacitance of the second semiconductor layer to a selected one of several predetermined voltages, the selected predetermined voltage being selected for one of:

program, program-inhibit, reading and erasing data of the storage transistors.

5. The memory structure of claim 4, wherein the second semiconductor layer serves as a shared virtual ground reference and the third semiconductor layer serves as a common bit line for the storage transistors in each NOR string.

6. The memory structure of claim 4 wherein charge stored in the charge-trapping material in each storage transistor represent data stored in the storage transistor, wherein the circuitry comprises voltage sources for providing the configurations of voltages to be imposed on the terminals of each storage transistor, so as to effectuate program, program-inhibit, reading or erasing data stored in the storage transistor.

7. The memory structure of claim 6, wherein said data represents more than one bit of binary information stored on each storage transistor.

8. The memory structure of claim 6, wherein said data represents a continuum of stored states in an analog memory.

9. The memory structure of claim 6, wherein the circuitry further comprises one or more sense amplifiers for sensing the data stored in the storage transistors.

10. The memory structure of claim 6 wherein, during a reading or a program operation, only the conductor associated with an addressed storage transistor of a NOR string is raised for a period of time to the selected predetermined voltage required for the reading or the program operation, with conductors associated with all other storage elements of the NOR string or pre-charge transistors of the NOR string held at a voltage below a threshold voltage of an erased storage transistor.

11. The memory structure of claim 10, wherein active strips on one or more planes other than on a plane associated with the addressed storage transistor have their second or third semiconductor layer floated or pre-charged to an inhibit voltage.

12. The memory structure of claim 10, wherein storage transistors associated with active strips on more than one plane are programmed in a single concurrent programming operation.

13. The memory structure of claim 12 wherein, during the concurrent programming operation, the second semiconductor layer of each active strip in each plane is appropriately pre-charged to the selected predetermined voltage associated with a program or program-inhibit operation, programming voltage pulses are then applied to one or more addressed conductors, and wherein the concurrent programming operation is terminated after all storage transistors associated with the addressed conductors are read-verified to have reached their respective intended programmed states.

14. The memory structure of claim 13, wherein the programming voltage is one of several programming voltages in a programming sequence, the programming voltages representing different data values.

15. The memory structure of claim 4 wherein the second semiconductor layer of each active strip in one or more planes is appropriately concurrently pre-charged to selected predetermined voltage associated with a reading operation, prior to carrying out one or more reading operations of addressed storage transistors in one or more of the planes.

16. The memory structure of claim 15 wherein the selected predetermined voltages of active strips on one or more planes serve as virtual ground voltage sources that are electrically isolated from each other, thereby substantially avoiding ground bounce or current spikes when a multiplicity of the addressed storage transistors are concurrently read.