3D semiconductor device and structure
First Claim
Patent Images
1. A 3D semiconductor device, comprising:
- a first layer comprising first transistors each comprising a single crystal silicon channel;
a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors,wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer overlaying said second transistors,wherein a plurality of said third transistors form a logic circuit, andwherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error; and
wherein said first layer thickness is less than one micron.
2 Assignments
0 Petitions
Accused Products
Abstract
A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.
24 Citations
20 Claims
-
1. A 3D semiconductor device, comprising:
-
a first layer comprising first transistors each comprising a single crystal silicon channel; a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors, wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer overlaying said second transistors, wherein a plurality of said third transistors form a logic circuit, and wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error; and wherein said first layer thickness is less than one micron. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A 3D semiconductor device, comprising:
-
a first layer comprising first transistors each comprising a single crystal silicon channel; a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors, wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer overlaying said second transistors, wherein a plurality of said third transistors form a logic circuit, and wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A 3D semiconductor device, comprising:
-
a first layer comprising first transistors each comprising a single crystal silicon channel; a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors, wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and a third layer comprising third transistors each comprising a single crystal silicon channel, said third structure overlaying said second transistors, wherein a plurality of said third transistors form a logic circuit, and wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error; and a memory control line, said memory control line is embedded in said second structure and comprises single crystal silicon. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeMonolithic 3D, Inc.
-
Original AssigneeMonolithic 3D, Inc.
-
InventorsOr-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
-
Primary Examiner(s)Schoenholtz, Joseph
-
Application NumberUS15/201,430Publication NumberTime in Patent Office591 DaysField of SearchNoneUS Class CurrentCPC Class CodesH01L 21/76254 with separation/delaminatio...H01L 21/8221 Three dimensional integrate...H01L 2224/16225 the item being non-metallic...H01L 2224/32225 the item being non-metallic...H01L 2224/73204 the bump connector being em...H01L 23/367 Cooling facilitated by shap...H01L 24/00 Arrangements for connecting...H01L 27/0688 Integrated circuits having ...H01L 27/085 including field-effect comp...H01L 27/0886 including transistors with ...H01L 27/092 complementary MIS field-eff...H01L 29/42392 fully surrounding the chann...H01L 2924/00 Indexing scheme for arrange...H01L 2924/15311 being a ball array, e.g. BGAH10B 10/125 the MOSFET being a thin fil...H10B 12/01 Manufacture or treatmentH10B 12/20 DRAM devices comprising flo...H10B 41/20 characterised by three-dime...H10B 41/35 with a cell select transist...H10B 61/20 comprising components havin...View All
