Vertical power MOSFET and methods of forming the same
First Claim
1. A method comprising:
- forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;
forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;
forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;
implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space;
forming a dielectric layer covering the first gate electrode and the second gate electrode;
forming a first field plate over the dielectric layer;
forming a source region, wherein a portion of the source region overlaps the doped semiconductor region;
forming an inter-layer dielectric between the first field plate and the source region; and
forming a drain region underlying the semiconductor layer; and
forming a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor layer, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, an HV P-type MOS (HVPMOS) device, and combinations thereof, wherein the forming the MOS containing device comprises;
when the first gate electrode and the second gate electrode are formed, simultaneously forming a third gate electrode for the MOS containing device; and
when the first field plate is formed, simultaneously forming a second field plate for the MOS containing device, with the second field plate having a portion overlapping the third gate electrode, and a portion level with the third gate electrode.
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Abstract
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.
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Citations
20 Claims
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1. A method comprising:
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forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising; forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type; forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space; implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space; forming a dielectric layer covering the first gate electrode and the second gate electrode; forming a first field plate over the dielectric layer; forming a source region, wherein a portion of the source region overlaps the doped semiconductor region; forming an inter-layer dielectric between the first field plate and the source region; and forming a drain region underlying the semiconductor layer; and forming a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor layer, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, an HV P-type MOS (HVPMOS) device, and combinations thereof, wherein the forming the MOS containing device comprises; when the first gate electrode and the second gate electrode are formed, simultaneously forming a third gate electrode for the MOS containing device; and when the first field plate is formed, simultaneously forming a second field plate for the MOS containing device, with the second field plate having a portion overlapping the third gate electrode, and a portion level with the third gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising; epitaxially growing an epitaxy semiconductor layer of a first conductivity type; forming a semiconductor body layer extending into the epitaxy semiconductor layer, wherein the semiconductor body layer is of a second conductivity type opposite the first conductivity type; forming a gate dielectric layer over the semiconductor body layer; forming a first and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space; implanting a portion of the semiconductor body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space, and wherein the doped semiconductor region extends to contact the epitaxy semiconductor layer; forming a dielectric layer over the first and the second gate electrodes; forming a first conductive field plate over the dielectric layer, wherein the first conductive field plate extends into the space between the first and the second gate electrodes; forming a source region over the semiconductor body layer; and forming a drain region underlying the epitaxy semiconductor layer; and forming a high voltage Metal-Oxide-Semiconductor (MOS) device at a surface of the epitaxy semiconductor layer, wherein the forming the high voltage MOS device comprises forming a second conductive field plate on a drain side of a gate electrode of the high voltage MOS device, and the first and the second conductive field plates are formed simultaneously. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method comprising:
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forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising; forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type; forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space, with an intermediate portion of the gate dielectric layer being in the space; implanting a portion of the body layer underlying the intermediate portion of the gate dielectric layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is implanted to a level lower than a bottom of the body layer; implanting an additional portion of the body layer to form a heavily doped region shallower than the body layer and the doped semiconductor region, with the heavily doped region being on an opposite side of the first gate electrode than the doped semiconductor region; forming a source region, wherein a portion of the source region overlaps the doped semiconductor region and the intermediate portion of the gate dielectric layer, and the source region contacts the heavily doped region; and forming a drain region underlying the semiconductor layer; and forming a high voltage Metal-Oxide-Semiconductor (MOS) device at a surface of the semiconductor layer comprising; when the doped semiconductor region is formed, simultaneously implanting an additional portion of the semiconductor layer to form an additional doped region for the high voltage MOS device. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification