Vertical power MOSFET and methods of forming the same

• US 9,892,974 B2
• Filed: 07/17/2015
• Issued: 02/13/2018
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US14/802,239
• Publication Number:
  US 20150325485A1
• Time in Patent Office: 942 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.

Claims

1. A method comprising:

forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;

forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space;

forming a dielectric layer covering the first gate electrode and the second gate electrode;

forming a first field plate over the dielectric layer;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region;

forming an inter-layer dielectric between the first field plate and the source region; and

forming a drain region underlying the semiconductor layer; and

forming a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor layer, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, an HV P-type MOS (HVPMOS) device, and combinations thereof, wherein the forming the MOS containing device comprises;

when the first gate electrode and the second gate electrode are formed, simultaneously forming a third gate electrode for the MOS containing device; and

when the first field plate is formed, simultaneously forming a second field plate for the MOS containing device, with the second field plate having a portion overlapping the third gate electrode, and a portion level with the third gate electrode.

2. The method of claim 1, wherein the gate dielectric layer extends into the space, and the implanting is performed with an implanted impurity penetrating through a portion of the gate dielectric layer in the space.

3. The method of claim 1 further comprising:

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode; and

etching portions of the body layer to expose sidewalls of the heavily doped regions.

4. The method of claim 3, wherein the source region comprises a metal, and the source region is in contact with sidewalls of the heavily doped regions.

5. The method of claim 1, wherein the forming the vertical power MOSFET comprises implanting a top portion of the semiconductor layer to convert the top portion to the body layer, and the forming the MOS containing device comprising, when the body layer is formed, simultaneously implanting an additional top portion of the semiconductor layer to form a doped region in a high-voltage well region of the MOS containing device.

6. The method of claim 1, wherein the source region comprises a portion filled into the space, with the portion level with the first gate electrode and the second gate electrode.

7. The method of claim 1, wherein the first field plate comprises a portion extending into the space and level with the first gate electrode and the second gate electrode.

8. The method of claim 1, wherein the doped semiconductor region penetrates through the body layer to contact the semiconductor layer.

9. A method comprising:

forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;

epitaxially growing an epitaxy semiconductor layer of a first conductivity type;

forming a semiconductor body layer extending into the epitaxy semiconductor layer, wherein the semiconductor body layer is of a second conductivity type opposite the first conductivity type;

forming a gate dielectric layer over the semiconductor body layer;

forming a first and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the semiconductor body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space, and wherein the doped semiconductor region extends to contact the epitaxy semiconductor layer;

forming a dielectric layer over the first and the second gate electrodes;

forming a first conductive field plate over the dielectric layer, wherein the first conductive field plate extends into the space between the first and the second gate electrodes;

forming a source region over the semiconductor body layer; and

forming a drain region underlying the epitaxy semiconductor layer; and

forming a high voltage Metal-Oxide-Semiconductor (MOS) device at a surface of the epitaxy semiconductor layer, wherein the forming the high voltage MOS device comprises forming a second conductive field plate on a drain side of a gate electrode of the high voltage MOS device, and the first and the second conductive field plates are formed simultaneously.

10. The method of claim 9, wherein the forming the high voltage MOS device comprises forming an additional semiconductor body layer over the epitaxy semiconductor layer, wherein the semiconductor body layer and the additional semiconductor body layer are formed simultaneously in a same process step.

11. The method of claim 9, wherein the implanting the portion of the semiconductor body layer is performed using the first and the second gate electrodes as an implantation mask.

12. The method of claim 9 further comprising, when the semiconductor body layer is formed, simultaneously forming an additional body layer for the high voltage MOS device.

13. The method of claim 9, wherein the dielectric layer comprises:

a first portion directly over a top surface of the first gate electrode;

a second portion directly over a top surface of the second gate electrode; and

a third portion in the space, wherein the third portion connects the first portion to the second portion.

14. The method of claim 9, wherein the source region and the first conductive field plate is physically separated from the source region by an inter-layer dielectric.

15. A method comprising:

forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;

forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space, with an intermediate portion of the gate dielectric layer being in the space;

implanting a portion of the body layer underlying the intermediate portion of the gate dielectric layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is implanted to a level lower than a bottom of the body layer;

implanting an additional portion of the body layer to form a heavily doped region shallower than the body layer and the doped semiconductor region, with the heavily doped region being on an opposite side of the first gate electrode than the doped semiconductor region;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region and the intermediate portion of the gate dielectric layer, and the source region contacts the heavily doped region; and

forming a drain region underlying the semiconductor layer; and

forming a high voltage Metal-Oxide-Semiconductor (MOS) device at a surface of the semiconductor layer comprising;

when the doped semiconductor region is formed, simultaneously implanting an additional portion of the semiconductor layer to form an additional doped region for the high voltage MOS device.

16. The method of claim 15 further comprising:

after the implanting the portion of the body layer to form the doped semiconductor region, forming a dielectric layer over the first and the second gate electrodes; and

forming a conductive field plate over the dielectric layer, wherein the conductive field plate extends into the space between the first and the second gate electrodes.

17. The method of claim 15 further comprising:

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode; and

etching portions of the body layer to expose sidewalls of the heavily doped regions.

18. The method of claim 17, wherein the source region comprises a metal, and the source region is in contact with the sidewalls of the heavily doped regions.

19. The method of claim 15, wherein the source region comprises a portion filled into the space, with the portion of the source region being level with the first gate electrode and the second gate electrode.

20. The method of claim 16, wherein the dielectric layer comprises a portion in the space, and the portion of the dielectric layer is directly underlying a portion of the conductive field plate extending into the space.