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Vertical power MOSFET and methods of forming the same

  • US 9,892,974 B2
  • Filed: 07/17/2015
  • Issued: 02/13/2018
  • Est. Priority Date: 06/01/2012
  • Status: Active Grant
First Claim
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1. A method comprising:

  • forming a vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;

    forming a gate dielectric layer over a body layer, wherein the body layer extends into a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

    forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

    implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space;

    forming a dielectric layer covering the first gate electrode and the second gate electrode;

    forming a first field plate over the dielectric layer;

    forming a source region, wherein a portion of the source region overlaps the doped semiconductor region;

    forming an inter-layer dielectric between the first field plate and the source region; and

    forming a drain region underlying the semiconductor layer; and

    forming a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor layer, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV)N-type MOS (HVNMOS) device, a Low Voltage (LV)N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, an HV P-type MOS (HVPMOS) device, and combinations thereof, wherein the forming the MOS containing device comprises;

    when the first gate electrode and the second gate electrode are formed, simultaneously forming a third gate electrode for the MOS containing device; and

    when the first field plate is formed, simultaneously forming a second field plate for the MOS containing device, with the second field plate having a portion overlapping the third gate electrode, and a portion level with the third gate electrode.

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