Flip-chip structure of group III semiconductor light emitting device

• US 9,893,040 B2
• Filed: 05/05/2016
• Issued: 02/13/2018
• Est. Priority Date: 05/05/2015
• Status: Active Grant

• Current Assignee: Xiangneng Hualei Optoelectronic Co., Ltd.
• Original Assignee: Xiangneng Hualei Optoelectronic Co., Ltd.
• Inventors: Xu, Shuncheng
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): IMTIAZ, S M SOHEL
• Application Number:
  US15/318,658
• Publication Number:
  US 20170117259A1
• Time in Patent Office: 649 Days
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

This application refers to a flip-chip structure of Group III semiconductor light emitting device. The flip-chip structure includes: a substrate, a buffer layer, nitride semiconductor layer, an active layer, a P type nitride semiconductor layer, a transparent conductive layer, a first insulation layer, a P type contact metal, a N type contact metal, a second insulation layer, a flip-chip P type electrode and a flip-chip N type electrode. The substrate, the buffer layer, the N type nitride semiconductor layer, the active layer, the P type nitride semiconductor layer which grow sequentially from bottom to top form a linear convex mesa. In this application, structure of the first insulation layer which is formed by aBraggs reflective layer, a metal layer and the multilayer oxide insulation layer, acts as a reflector structure and an insulation layer to replace the flip-chip reflector structure design and the first insulation layer, so that a metal protective layer can be omitted.

Claims

1. A flip-chip structure of III group semiconductor light emitting device comprising:

a substrate, a buffer layer, a N type nitride semiconductor layer, an active layer, a P type nitride semiconductor layer, a transparent conductive layer, a first insulation layer structure, a P type contact metal, a N type contact metal, a second insulation layer structure, a flip-chip P type electrode and a flip-chip N type electrode, wherein the substrate, the buffer layer, the N type nitride semiconductor layer, the active layer, the P type nitride semiconductor layer which grow sequentially from bottom to top form a linear convex mesa;

wherein the linear convex mesa comprises a first top surface, a side surface and a second top surface, the first top surface of the linear convex mesa and the second top surface of the linear convex mesa individually connects with the side surface to form a L shape structure, the first top surface of the linear convex mesa being the top surface of the P type nitride semiconductor layer, the second top surface of the linear convex mesa being the top surface of the N type nitride semiconductor layer;

the transparent conductive layer located on top of the first top surface of the linear convex mesa;

the first insulation layer structure located on the first top surface of the linear convex mesa, the side surface, the second top surface of the linear convex mesa and the surface of the transparent conductive layer;

a bottom end of the P type contact metal is located between the first insulation layer structure and the transparent conductive layers or on the transparent conductive layer;

a bottom end of the N type contact metal located between the first insulation layer structure and the second top surfaces or on the second top surface of the linear convex mesa;

the second insulation layer structure located on the first insulation layer structure, the top surface of the P type contact metal and the N type contact metal;

a bottom end of the flip-chip P type electrode located on the surface of the P type contact metal and the second insulation layer structure;

a bottom end of the flip-chip N type electrode located on the surface of the N type contact metal and the second insulation layer structure,

wherein the flip-chip structure has an isolation groove, which is located around the flip-chip structure, the isolation groove is attained by way of etching to expose the substrate, the surface of the isolation groove has the first insulation layer structure and/or the second insulation layer structure,

the first insulation layer structure formed by the single-layer oxide insulation layer, the multilayer oxide insulation layer, and a Braggs reflective layer-metal layer-single layer oxide insulation layer or formed by a Braggs reflective layer-metal layer-multilayer oxide insulation layer.

2. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the material of the single-layer oxide insulation layer is one of aluminum oxide, silicon oxide, titanium oxide, tantalic oxide, niobium oxide and silicon nitride, the material of the multilayer oxide insulation layer is at least two of the aluminum oxide, silicon oxide, titanium oxide, tantalic oxide, niobium oxide, silicon oxide and silicon nitride.

3. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the thickness of each layer of single-layer oxide insulation layer or the thickness of each layer of the multilayer oxide insulation layer is in a range of 30-200 nm.

4. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the Braggs reflective layer is formed by silicon oxide and titanium oxide, or formed by silicon oxide and tantalic oxide, or formed by silicon oxide and niobium oxide;

wherein the thickness of the silicon oxide is in a range of 30-1000 nm, the thickness of the titanium oxide is in a range of 10-200 nm, the thickness of the tantalic oxide is in a range of 10-200 nm, the thickness of niobium oxide is in a range of 10-200 nm.

5. The flip-chip structure of III group semiconductor light emitting device as defined in claim 4, wherein the Braggs reflective layer is formed by 3.5 pairs of silicon dioxide/titanium dioxide/silicon dioxide/titanium dioxide/silicon dioxide/titanium dioxide/silicon dioxide, or formed by 3.5 pairs of silicon dioxide/tantalic oxide/silicon dioxide/tantalic oxide/silicon dioxide/tantalic oxide/silicon dioxide, or formed by 3.5 pairs of silicon dioxide/niobium oxide/silicon dioxide/niobium oxide/silicon dioxide/niobium oxide/silicon dioxide.

6. The flip-chip structure of III group semiconductor light emitting device as defined in claim 5, wherein when the first insulation layer structure is stacked by the Braggs reflective layer-metal layer-single-layer oxide insulation layer or stacked by the Braggs reflective-metal layer-multilayer oxide insulation layer, the bottom end of the metal layer is located on the top surface of the Braggs reflective layer of the first insulation layer structure, and/or is located in the multilayer oxide insulation layer of the first insulation layer structure.

7. The flip-chip structure of III group semiconductor light emitting device as defined in claim 6, wherein the material of the metal layer is at least one of the silver, aluminum, silver indium, platinum, nickel and titanium, wherein each thickness of the silver, the aluminum, the silver indium and the platinum is in a range of 50-500 nm, each thickness of the nickel and titanium is in a range of 0.3-30 nm.

8. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the bottom end of the P type contact metal is located on the surface of the first insulation layer structure and the transparent conductive layer, the bottom end of the N type contact metal is located on the surface of the first insulation layer structure and the second top surface of the linear convex mesa.

9. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the P type contact metal comprises a P type linear electrode and a P type solder pad;

the bottom end of the P type solder pad is located on the surface of the first insulation layer structure, the bottom end of the P type linear electrode is located on the transparent conductive layer or on both surfaces of the first insulation layer structure and the transparent conductive layer;

the N type contact metal comprises N type linear electrode and a N type solder pad, the bottom end of the N type solder pad is located on the surface of the first insulation layer structure, the bottom end of the N type linear electrode is located on the second top surface of the linear convex mesa or on both surfaces of the first insulation layer structure and the second top surface of the linear convex mesa.

10. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the P type contact metal comprises a P type linear electrode and a P type contact metal, the bottom end of the P type linear electrode is located on the transparent conductive layer or on both surfaces of the first insulation layer structure and transparent conductive layer, the bottom end of the P type contact metal is located on the surface of the first insulation layer structure;

the N type contact metal comprises N type linear electrode and N type connection metal, the bottom end of the N type linear electrode is located on the second top surface of the linear convex mesa or on both surfaces of the first insulation layer structure and the second top surface of the linear convex mesa, the bottom end of the N type connection metal is located on the surface of the first insulation layer structure.

11. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein both structures of the P type contact metal and the N type contact metal are formed are formed by single-layer metal layer or multilayer metal layer;

when both structures of the P type metal layer and the N type metal layer are formed by the single-layer, the material of the single-layer metal layer consists of at least one of aluminum, titanium, platinum, gold, rhodium, tungsten, nickel, silver or silver indium, the thickness of the single-layer metal layer is in a range of 50-3000 nm;

when both structures of the P type metal layer and the N type metal layer are formed by multilayer metal layers, which sequentially comprises a first metal layer, a middle metal layer and an end metal layer, therein the material of the first metal layer comprises one of nickel, titanium, chromium, the material of the middle metal layer comprises at least one of aluminum, titanium, chromium, platinum, gold, rhodium, tungsten, nickel, silver, or silver indium, the material of the end metal layer comprises one of nickel, titanium and chromium, and the thickness of the first metal layer is in a range of 0.3-300 nm, the thickness of each layer of the middle metal layer is in a range of 10-3000 nm, the thickness of the end metal layer is in a range of 0.3-300 nm.

12. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein the second insulation layer structure is formed by a single-layer oxide insulation layer or a multilayer oxide insulation layer, wherein the material of the single-layer oxide insulation layer is formed by one of aluminum oxide, silicon dioxide, titanium dioxide, tantalic oxide, niobium oxide, silicon oxide and silicon nitride, the multilayer oxide insulation is formed by at least two of the combinations of aluminum oxide, silicon dioxide, titanium dioxide, tantalic oxide, niobium oxide, silicon oxide and silicon nitride, a thickness of each layer of the single-layer oxide insulation layer and the multilayer oxide insulation is in a range of 30-2000 nm.

13. The flip-chip structure of III group semiconductor light emitting device as defined in claim 1, wherein both structures of the flip-chip P type electrode and the flip-chip N type electrode sequentially comprise a Ti layer, a second Ni layer, an Au layer from inner to outer, or sequentially comprise a middle Cr layer, a Pt layer, an Au layer, the second Ni layer, a Pt layer, the second Ni layer, an Au—

Sn layer from inner to outer;

or sequentially comprise a first Ni layer, an Al layer, the second Ni layer, the Au layer from inner to outer;

or sequentially comprise the middle Cr layer, the Pt layer, the Au layer from inner to outer;

or sequentially comprise the middle Cr layer, the second Ni layer and the Au layer from inner to outer;

or sequentially comprise a first Ni layer, the Al layer, the middle Cr layer, the second Ni layer and the Au layer from inner to outer;

or sequentially comprise a first Ni layer, the Al layer, the middle Cr layer, the Pt layer and the Au layer from inner to outer;

or sequentially comprise a first Ni layer, the Al layer, the second Ni layer, the Pt layer and the Au layer from inner to outer;

or sequentially comprise a first Ni layer, the Al layer, the Ti layer, the Pt layer and the Au layer from inner to outer;

or sequentially comprise a first Cr layer, the Al layer, the middle Cr layer, the Pt layer and the Au layer from inner to outer;

or sequentially comprise a first Cr layer, the Al layer, the Ni layer, the Pt layer and the Au layer from inner to outer;

therein the thickness of the first Ni layer is in a range of 0.4-3 nm, the thickness of the second Ni layer is in a range of 10-300 nm, the thickness of the Ti layer is in a range of 10-300 nm, the thickness of the Al layer is in a range of 50-300 nm, the thickness of the Au layer is in a range of 20-3000 nm, the thickness of the first Cr layer is in a range of 0.4-5 nm, the thickness of the middle Cr layer is in a range of 10-300 nm, the thickness of the Pt layer is in a range of 10-300 nm, the thickness of the Au—

Sn layer is in a range of 1000-5000 nm.