Memory device having electrically floating body transistor
First Claim
1. A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;
wherein said back bias region is commonly connected to at least two of said memory cells, andwherein said back bias region has a lower band gap than said floating body region.
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
239 Citations
20 Claims
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1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; and a back-bias region configured to maintain a charge in said floating body region; wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity; wherein said back bias region is commonly connected to at least two of said memory cells, and wherein said back bias region has a lower band gap than said floating body region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back-bias region located below said floating body region; wherein said back-bias region acts as a collector region of a bipolar transistor that maintains the state of said memory cell and has a lower band gap than said floating body region, and wherein said back bias region is commonly connected to at least two of said memory cells. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region storing a charge or lack of charge indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions; a back-bias region commonly connected to at least two of said memory cells, wherein said back bias region has a lower band gap than said floating body region; and wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of a back bias via said back-bias region generates impact ionization in one of said first and second memory cells, and not in the other of said first and second memory cells. - View Dependent Claims (17, 18, 19, 20)
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Specification