Semiconductor memory device

• US 9,893,078 B2
• Filed: 02/24/2015
• Issued: 02/13/2018
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Minami, Toshifumi, Sato, Atsuhiro, Yonehama, Keisuke, Baba, Yasuyuki, Shinohara, Hiroshi, Kamata, Hideyuki, Higashitsuji, Teppei
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US14/630,507
• Publication Number:
  US 20160071870A1
• Time in Patent Office: 1,085 Days
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Claims

1. A semiconductor memory device comprising:

a conductive layer and an insulating layer that are disposed above a semiconductor substrate;

a first plate that extends through the conductive layer and the insulating layer in a first direction which crosses a surface of the semiconductor substrate and also extends in a second direction perpendicular to the first direction;

a second plate that extends through the conductive layer and the insulating layer in the first direction and also extends in the second direction, and is spaced apart from the first plate in a third direction perpendicular to the first and second directions; and

a plurality of pillars that extend through the conductive layer and the insulating layer in the first direction and are between the first and second plates in the third direction

wherein a surface of the first plate has convex portions and non-convex portions, and a surface of the second plate has convex portions and non-convex portions, and

wherein the surface of first plate faces each of the plurality of pillars with no other pillar between the first plate and said each pillar, and the surface of second plate faces each of the plurality of pillars with no other pillar between the second plate and said each pillar.

2. The device according to claim 1,

wherein respective center points of the convex portions of the first and second plates are aligned in the third direction and are not aligned with any center point of the pillars in the third direction.

3. The device according to claim 2,

wherein a first distance between a center point of one of the convex portions and a center point of the pillar that is closest thereto is substantially equal to a second distance between respective center points of adjacent pillars.

4. The device according to claim 3,

wherein a third distance between respective center points of adjacent convex portions is substantially equal to the first and second distances.

5. The device according to claim 1, further comprising:

an insulating film that surrounds each of the pillars,

wherein a gap between one of the convex portions and the insulating film of the pillar that is closest thereto is smaller than a gap between one of the non-convex portions and the insulating film of the pillar that is closest thereto.

6. The device according to claim 1, further comprising:

an insulating film that surrounds each of the pillars,

wherein each of the convex portions has substantially the same outer dimension as each insulating film surrounding one of the pillars.

7. The device according to claim 1, wherein the non-convex portions each have a substantially flat surface.

8. The device according to claim 1, further comprising:

a back gate layer in contact with the surface of the semiconductor substrate;

a lower insulating layer between the conductive layer and the back gate layer; and

an etch stop layer formed in the lower insulating layer, the plate extending through the conductive layer and the insulating layer and stopping at the etch stop layer.

9. The device according to claim 8, further comprising:

a selection gate layer above the conductive layer and the insulating layer,

wherein the plate extends through the selection gate layer.

10. The device according to claim 9, further comprising:

a plurality of additional conductive layers and additional insulating layers alternately stacked between the selection gate layer and the lower insulating layer,

wherein the plate extends through the additional conductive layers and the additional insulating layers.

11. A semiconductor memory device comprising:

a conductive layer and an insulating layer that are disposed above a semiconductor substrate;

a plurality of pillars that extend in a first direction which crosses a surface of the semiconductor substrate;

a plate that is disposed between the plurality of pillars and extends in the first direction;

a back gate layer in contact with the surface of the semiconductor substrate;

a lower insulating layer between the conductive layer and the back gate layer; and

an etch stop layer formed in the lower insulating layer, the plate extending through the conductive layer and the insulating layer and stopping at the etch stop layer,

wherein a surface of the plate, which faces the pillars, has convex portions and non-convex portions.

12. The device according to claim 11,

wherein respective center points of the convex portions of the plate and respective center points of the pillars are disposed in a regular array above the surface of the semiconductor substrate.

13. The device according to claim 12,

wherein a first distance between a center point of the convex portion of the plate and a center point of the pillar closest to the convex portion is substantially equal to a second distance between respective center points of adjacent pillars.

14. The device according to claim 13,

wherein a third distance between respective center points of adjacent convex portions is substantially equal to the first and second distances.

15. The device according to claim 11, further comprising:

an insulating film that surrounds each of the pillars,

wherein a gap between a convex portion of the plate and the insulating film of the pillar closest to the convex portion is smaller than a gap between a non-convex portion of the plate and the insulating film of the pillar closest to the non-convex portion.

16. The device according to claim 11, further comprising:

an insulating film that surrounds each of the pillars,

wherein each of the convex portions has substantially the same outer dimension as each insulating film surrounding one of the pillars.

17. The device according to claim 11, wherein the non-convex portions each have a substantially flat surface.

18. The device according to claim 11, further comprising:

a selection gate layer above the conductive layer and the insulating layer,

wherein the plate extends through the selection gate layer.

19. The device according to claim 18, further comprising:

a plurality of additional conductive layers and additional insulating layers alternately stacked between the selection gate layer and the lower insulating layer,

wherein the plate extends through the additional conductive layers and the additional insulating layers.