Method for fabricating a transistor device with a tuned dopant profile

• US 9,893,148 B2
• Filed: 10/04/2016
• Issued: 02/13/2018
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Bakhishev, Teymur, Pradhan, Sameer, Hoffmann, Thomas, Sonkusale, Sachin R.
• Primary Examiner(s): Payen, Marvin
• Application Number:
  US15/285,279
• Publication Number:
  US 20170025501A1
• Time in Patent Office: 497 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Claims

1. A transistor device having a gate, a channel, a source and a drain on either side of the channel, comprising:

an anti-punchthrough layer in a semiconductor substrate;

a screening layer above the anti-punchthrough layer, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;

a dopant migration mitigating material above the anti-punchthrough layer, the dopant migration mitigating material reducing a dopant migration of the screening layer;

a substantially undoped layer above the screening layer, the channel is formed in the substantially undoped layer; and

wherein a dopant profile of the screening layer has a peak of which position is shallower than a position of a peak in a dopant profile of the dopant migration mitigating material.

2. The method of claim 1, comprising:

a threshold voltage set layer above the screening layer;

wherein the threshold voltage set layer is coextensive with the screening layer and abuts the source and drain and the screening layer extends laterally across the channel.

3. The transistor device of claim 1, wherein the dopant migration mitigating material comprises carbon.