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Method for fabricating a transistor device with a tuned dopant profile

  • US 9,893,148 B2
  • Filed: 10/04/2016
  • Issued: 02/13/2018
  • Est. Priority Date: 03/14/2013
  • Status: Active Grant
First Claim
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1. A transistor device having a gate, a channel, a source and a drain on either side of the channel, comprising:

  • an anti-punchthrough layer in a semiconductor substrate;

    a screening layer above the anti-punchthrough layer, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;

    a dopant migration mitigating material above the anti-punchthrough layer, the dopant migration mitigating material reducing a dopant migration of the screening layer;

    a substantially undoped layer above the screening layer, the channel is formed in the substantially undoped layer; and

    wherein a dopant profile of the screening layer has a peak of which position is shallower than a position of a peak in a dopant profile of the dopant migration mitigating material.

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