Semiconductor device and method of manufacturing the same

• US 9,893,153 B2
• Filed: 07/30/2015
• Issued: 02/13/2018
• Est. Priority Date: 09/19/2014
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimizu, Tatsuo
• Primary Examiner(s): Kim, Su C
• Application Number:
  US14/813,619
• Publication Number:
  US 20160087045A1
• Time in Patent Office: 929 Days
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/3211 Nitridation of silicon-containing layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, a first region provided between the SiC layer and the gate insulating film, and a second region provided in the SiC layer. The first region contains at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine). The second region provided adjacent to the first region, and the second region has a higher oxygen concentration than a concentration of the at least one element.

Claims

1. A semiconductor device comprising:

a SiC layer;

a gate electrode;

a gate insulating film provided between the SiC layer and the gate electrode;

a first region provided between the SiC layer and the gate insulating film, the first region containing at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine); and

a second region being an uppermost part of the SiC layer, being not thermally oxidized SiC, and being provided adjacent to the first region, an oxygen concentration in the second region being higher than a concentration of the at least one element in the second region.

2. The device according to claim 1, wherein the SiC layer is of a p-type.

3. The device according to claim 1, wherein a distance between a boundary between the first region and the second region, and a peak position of the concentration of the at least one element in the first region is 5 nm or shorter.

4. The device according to claim 1, wherein the oxygen concentration in the second region is not lower than 1×

10¹⁶ cm<sup>−

3</sup> and not higher than 1×

10²¹ cm<sup>−

3</sup>.

5. The device according to claim 1, wherein a Si—

O—

Si bond exists in the second region.

6. The device according to claim 1, wherein carbon site in a SiC lattice is occupied by oxygen in the second region.

7. The device according to claim 1, wherein a peak concentration of the at least one element in the first region is not lower than 1×

10¹⁸ cm<sup>−

3</sup> and not higher than 1×

10²³ cm<sup>−

3</sup>.

8. The device according to claim 1, wherein the gate insulating film is a silicon oxide film.

9. The device according to claim 1, wherein the second region includes a pair of oxygen atoms occupying a carbon site of SiC lattice.

10. A semiconductor device comprising:

a SiC layer;

a gate electrode;

a gate insulating film provided between the SiC layer and the gate electrode;

a first region provided between the SiC layer and the gate insulating film, the first region containing at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine), and

a second region being a part of the SiC layer, being single crystal SiC, being a conductive channel forming region, and being provided adjacent to the first region, an oxygen concentration in the second region being higher than a concentration of the at least one element in the second region.

11. The device according to claim 10, wherein the SiC layer is of a p-type.

12. The device according to claim 10, wherein a distance between a boundary between the first region and the second region, and a peak position of the concentration of the at least one element in the first region is 5 nm or shorter.

13. The device according to claim 10, wherein the oxygen concentration in the second region is not lower than 1×

10¹⁶ cm<sup>−

3</sup> and not higher than 1×

10²¹ cm<sup>−

3</sup>.

14. The device according to claim 10, wherein a Si—

O—

Si bond exists in the second region.

15. The device according to claim 10, wherein carbon site in a SiC lattice is occupied by oxygen in the second region.

16. The device according to claim 10, wherein a peak concentration of the at least one element in the first region is not lower than 1×

10¹⁸ cm<sup>−

3</sup> and not higher than 1×

10²³ cm<sup>−

3</sup>.

17. The device according to claim 10, wherein the gate insulating film is a silicon oxide film.

18. The device according to claim 10, wherein the second region includes a pair of oxygen atoms occupying a carbon site of the SiC lattice.

19. The device according to claim 10, wherein the second region includes a pair of oxygen atoms occupying a carbon site of SiC lattice.