Recess liner for silicon germanium fin formation

• US 9,893,154 B2
• Filed: 05/31/2017
• Issued: 02/13/2018
• Est. Priority Date: 04/11/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: McArdle, Timothy J., Holt, Judson R., Wang, Junli
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US15/609,295
• Publication Number:
  US 20170294515A1
• Time in Patent Office: 258 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66 : Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.

Claims

1. A semiconductor device comprising:

at least one fin having a first conductivity extended above a first region of a substrate structure, and at least one fin having a second conductivity extended above a second region of the substrate structure, wherein a first fin of the at least one fin having the second conductivity has a graded germanium concentration.

2. The semiconductor device of claim 1, wherein a total height of the at least one fin extended above the first region of the substrate structure is equal to a total height of the at least one fin extended above the second region of the substrate structure.

3. The semiconductor device of claim 1, wherein the at least one fin extended above the first region of the substrate structure comprises a silicon material, and the at least one fin extended above the second region of the substrate structure comprises a silicon germanium material.

4. The semiconductor device of claim 1, wherein the first region of the substrate structure comprises a p-type field-effect transistor (PFET) device region, and the second region of the substrate structure comprises an n-type field-effect transistor (NFET) device region.

5. The semiconductor device of claim 1, wherein a fin pitch of each of the at least one fin of the first region and the at least one fin of the second region is within a range from about 5 nm to about 50 nm.

6. The semiconductor device of claim 1, wherein the concentration of germanium within the first fin of the at least one fin having the second conductivity decreases relative to a concentration of germanium within a second fin of the at least one fin having the second conductivity.

7. The semiconductor device of claim 1, wherein the first fin extended above the second region is laterally adjacent to the at least one fin having a first conductivity extended above the first region.