Split gate semiconductor device with curved gate oxide profile

• US 9,893,168 B2
• Filed: 08/15/2016
• Issued: 02/13/2018
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Gao, Yang, Chen, Kuo-In, Terrill, Kyle, Shi, Sharon
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/237,259
• Publication Number:
  US 20160359018A1
• Time in Patent Office: 547 Days
• Field of Search: 438259, 438270, 438271, 438589, 438429, 438430, 438431, 257330, 257331, 257332, 257E29262
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

Claims

1. A method of fabricating a split gate in a semiconductor device, said method comprising:

forming a trench gate within a trench-like cavity in said semiconductor device, wherein said forming said trench gate comprises;

forming a first layer comprising a thermal oxide layer and a first dielectric region along sidewalls of said trench-like cavity, wherein said thermal oxide layer is along the bottom surface and surfaces of said sidewalls of said trench-like cavity, and wherein said first dielectric region is over said thermal oxide layer;

forming a first gate electrode region within said cavity and adjacent said first dielectric region;

removing a portion of said first layer from said sidewalls so that the height of said first layer is less than the height of said first gate electrode region;

forming a second dielectric region within said cavity and adjacent said first dielectric layer and said first gate electrode region, said second dielectric region having a uniform composition throughout;

etching back said second dielectric region to form a concave surface that traverses the entire width of said trench-like cavity, said concave surface highest where it meets said sidewalls of said trench-like cavity;

forming a gate oxide layer adjacent said second dielectric layer on said concave surface, wherein the boundary of said gate oxide layer and said second dielectric region is thereby concave; and

forming a second gate electrode region within said cavity and adjacent said gate oxide layer.

2. The method of claim 1 wherein said a gate oxide layer is also formed along said sidewalls prior to forming said second gate electrode region.

3. The method of claim 1 further comprising forming source and drain regions.

4. The method of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor (MOSFET) device.

5. A method of fabricating a split gate in a semiconductor device, said method comprising:

producing a thermal oxide layer along the bottom surface and sidewall surfaces of a trench;

forming a first dielectric region over the thermal oxide layer to form a first layer comprises said thermal oxide layer and said first dielectric region;

forming a first gate electrode region over said first dielectric region;

removing portions of said first layer from said sidewall surfaces so that the height of said first layer is less than the height of said first gate electrode region;

forming a second dielectric region in said trench by depositing a dielectric layer over said first layer and said first gate electrode region;

etching back said second dielectric region to form a concave surface that extends across the entire width of said trench and that meets said sidewall surfaces of said trench, wherein said concave surface is highest relative to said bottom surface of said trench where it meets said sidewalls of said trench;

forming a gate oxide layer adjacent said second dielectric region on said concave surface, wherein the boundary of said gate oxide layer and said second dielectric region is thereby concave; and

forming a second gate electrode region within said trench.

6. The method of claim 5 wherein said gate oxide layer is also formed along said sidewall surfaces prior to said step of forming said second gate electrode region.

7. The method of claim 5 further comprising forming source and drain regions.

8. The method of claim 5 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor (MOSFET) device.

9. The method of claim 5 wherein a same material is present throughout said second dielectric region.