Silicon-carbide trench gate MOSFETs
First Claim
Patent Images
1. An apparatus comprising:
- a silicon-carbide (SiC) substrate of a first conductivity type;
a drift region of the first conductivity type disposed on the SiC substrate;
a junction field-effect transistor (JFET) channel region of the first conductivity type disposed on the drift region;
a shielding body region of a second conductivity type disposed in the JFET channel region;
a channel stopper layer of the second conductivity type disposed on the shielding body region;
a source region of the first conductivity type disposed on the channel stopper layer;
a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface;
a built-in channel of the first conductivity type disposed below the gate trench, the built-in channel having a sidewall portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the built-in channel having a doping concentration that is different than a doping concentration of the JFET channel region;
a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and
a gate electrode disposed on the gate dielectric.
9 Assignments
0 Petitions
Accused Products
Abstract
In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.
-
Citations
21 Claims
-
1. An apparatus comprising:
-
a silicon-carbide (SiC) substrate of a first conductivity type; a drift region of the first conductivity type disposed on the SiC substrate; a junction field-effect transistor (JFET) channel region of the first conductivity type disposed on the drift region; a shielding body region of a second conductivity type disposed in the JFET channel region; a channel stopper layer of the second conductivity type disposed on the shielding body region; a source region of the first conductivity type disposed on the channel stopper layer; a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface; a built-in channel of the first conductivity type disposed below the gate trench, the built-in channel having a sidewall portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the built-in channel having a doping concentration that is different than a doping concentration of the JFET channel region; a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and a gate electrode disposed on the gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 21)
-
-
15. An apparatus comprising:
-
a silicon-carbide (SiC) substrate of a first conductivity type; a drift region of the first conductivity type disposed in the SiC substrate; a junction field-effect transistor (JFET) channel region of the first conductivity type disposed in the SiC substrate above the drift region; a shielding body region of a second conductivity type disposed in the JFET channel region; a channel stopper layer of the second conductivity type disposed on the shielding body region; a source region of the first conductivity type disposed on the channel stopper layer; a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface, the sidewall of the gate trench defining an angle of greater than 90 degrees with the bottom surface of the gate trench; a built-in channel of the first conductivity type disposed below the gate trench, the built-in channel having a sidewall portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the lateral portion of the built-in channel having a threshold voltage that is less than a threshold voltage of the sidewall portion of the built-in channel; a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and a gate electrode disposed on the gate dielectric within the gate trench. - View Dependent Claims (16, 17, 18)
-
-
19. An apparatus comprising:
-
a silicon-carbide (SiC) substrate of a first conductivity type; a drift region of the first conductivity type disposed in the SiC substrate; a junction field-effect transistor (JFET) channel region of the first conductivity type disposed in the SiC substrate above the drift region; a shielding body region of a second conductivity type disposed in the JFET channel region; a channel stopper layer of the second conductivity type disposed on the shielding body region; a source region of the first conductivity type disposed on the channel stopper layer; a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface, the sidewall of the gate trench defining an angle of approximately 90 degrees with the bottom surface of the gate trench; a built-in channel of the first conductivity type disposed below the gate trench, the built-in channel having a vertical portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the lateral portion of the built-in channel having a threshold voltage that is less than a threshold voltage of the vertical portion of the built-in channel, the vertical portion of the built-in channel being disposed below the channel stopper layer; a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and a gate electrode disposed on the gate dielectric within the gate trench. - View Dependent Claims (20)
-
Specification