Semiconductor device having a channel separation trench

• US 9,893,178 B2
• Filed: 06/21/2016
• Issued: 02/13/2018
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Schloesser, Till, Hirler, Franz
• Primary Examiner(s): Pizarro, Marcos D
• Assistant Examiner(s): GARCES, NELSON Y
• Application Number:
  US15/187,889
• Publication Number:
  US 20160300944A1
• Time in Patent Office: 602 Days
• Field of Search: 257330-340
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.

Claims

1. A semiconductor device comprising a transistor formed in a semiconductor substrate having a main surface, the transistor comprising:

a source region of a first conductivity type;

a drain region of the first conductivity type;

a channel region of a second conductivity type;

a gate trench adjacent to a first sidewall of the channel region;

a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal; and

a channel separation trench adjacent to a second sidewall of the channel region, the second sidewall facing the first sidewall via the channel region, the channel separation trench being filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region,

wherein the source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface.

2. The semiconductor device of claim 1, wherein a conductive inversion layer is formed along the first sidewall in an on-state.

3. The semiconductor device of claim 1, further comprising a drift zone between the channel region and the drain region.

4. The semiconductor device of claim 1, further comprising a field plate disposed in a field plate trench.

5. An integrated circuit comprising the semiconductor device of claim 1.

11. The semiconductor device according to claim 1, wherein the second sidewall extends along the first direction.

12. The semiconductor device according to claim 1, wherein the channel separation trench is arranged in the channel region.

6. A semiconductor device comprising an array of transistors formed in a semiconductor substrate having a main surface, the array of transistors comprising:

a source region of a first conductivity type;

a drain region of the first conductivity type;

a plurality of channel regions of a second conductivity type;

a plurality of trenches adjacent to each of the channel regions, respectively, so that two trenches are adjacent to opposite sides of one of the channel regions, respectively, the plurality of trenches including gate trenches and channel separation trenches; and

a gate conductive material connected to a gate terminal, the gate conductive material being disposed in the gate trenches,

wherein the gate trenches are arranged between the source region and the drain region along a first direction, the first direction being parallel to the main surface,

wherein at least one of the trenches is a channel separation trench, the channel separation trench being either filled with a dielectric material or being filled with a combination of a dielectric layer and a conductive filling disconnected from the gate terminal, the dielectric layer insulating a corresponding one of the channel regions from the conductive filling.

7. The semiconductor device of claim 6, wherein the gate trenches and the channel separation trenches are disposed in an alternating manner so that one gate trench and one channel separation trench is adjacent to different sidewalls of each of the channel regions.

8. An integrated circuit comprising the semiconductor device of claim 6.

13. The semiconductor device according to claim 6, further comprising a drift zone between the channel region and the drain region, the channel separation trench contacting the drift zone.

9. A semiconductor device comprising a transistor formed in a semiconductor substrate having a main surface, the transistor comprising:

a source region of a first conductivity type;

a drain region of the first conductivity type;

a channel region of a second conductivity type;

a drift zone between the channel region and the drain region;

a gate trench adjacent to a first sidewall of the channel region;

a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal; and

a channel separation trench adjacent to a second sidewall of the channel region, the second sidewall facing the first sidewall via the channel region, the channel separation trench having a conductive filling that is disconnected from the gate terminal, the channel separation trench contacting the drift zone,

wherein the gate trench is arranged between the source region and the drain region along a first direction, the first direction being parallel to the main surface, further comprising a dielectric layer in the channel separation trench, the dielectric layer insulating a corresponding one of the channel regions from the conductive filling.

10. The semiconductor device of claim 9, further comprising a field plate disposed in a field plate trench.

14. The semiconductor device according to claim 9, wherein the second sidewall extends along the first direction.