Semiconductor device

• US 9,893,180 B2
• Filed: 09/22/2016
• Issued: 02/13/2018
• Est. Priority Date: 09/07/2009
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Mitani, Shuhei, Nakano, Yuki, Watanabe, Heiji, Shimura, Takayoshi, Hosoi, Takuji, Kirino, Takashi
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US15/273,230
• Publication Number:
  US 20170012123A1
• Time in Patent Office: 509 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0445 the devices having semiconductor bodies comprising crystalline silicon carbide multistep processes for the manufacture of said devices H01L29/66053
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Claims

1. A semiconductor device, comprising:

a semiconductor layer that is of a first conductivity type;

a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and that has a channel region defined therein;

a source region that is a first conductivity type source region formed on a surface layer portion of the well region;

a gate insulating film formed on the semiconductor layer and having a multilayer structure;

a gate electrode opposed to the channel region of the well region where a channel is formed through the gate insulating film; and

a trench formed in the semiconductor layer that extends downwardly from the upper surface of the source region to pass through the source region and the well region, wherein

the gate insulating film is formed on the inner surface of the trench and includes a bump portion which changes a thickness of the gate insulating film at the source region, the bump portion being formed on a side surface of the trench, and being adjacent to the channel region, the magnitude of the bump portion being about 0.1 μ

m.

2. The semiconductor device according to claim 1, wherein the upper end of the gate insulating film is covered by an interlayer dielectric film.

3. The semiconductor device according to claim 1, wherein the gate insulating film includes a silicon oxide film.

4. The semiconductor device according to claim 3, wherein the gate insulating film further includes an aluminum oxynitride film on the silicon oxide film opposite to the source region and the aluminum oxynitride film silicon has no bump.

5. The semiconductor device according to claim 1, further comprising a contact region that is a second conductivity type contact region formed to pass through the source region.

6. The semiconductor device according to claim 2, further comprising source metal which covers the interlayer dielectric film and the source region from above.

7. The semiconductor device according to claim 1, wherein the gate electrode is made of metallic material and is embedded in the trench.

8. The semiconductor device according to claim 1, further comprising a semiconductor substrate that is a first conductivity type SiC substrate with respect to the semiconductor layer opposite to the well region.

9. A semiconductor device, comprising:

a semiconductor layer that is of a first conductivity type;

a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and that has a channel region defined therein;

a source region that is a first conductivity type source region formed on a surface layer portion of the well region;

a gate insulating film formed on the semiconductor layer and having a multilayer structure, the gate insulating film including a silicon oxide film and an aluminum oxynitride film on the silicon oxide film opposite to the source region, the aluminum oxynitride film having no bump; and

a gate electrode opposed to the channel region of the well region where a channel is formed through the gate insulating film.