Fin-type field effect transistor device and method of fabricating the same

• US 9,893,184 B2
• Filed: 12/15/2015
• Issued: 02/13/2018
• Est. Priority Date: 12/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US14/968,920
• Publication Number:
  US 20170170316A1
• Time in Patent Office: 791 Days
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

In accordance with some embodiments of the present disclosure, a fin-FET device includes a substrate, a stack structure, a source and drain region, a sidewall insulator and a metal connector. The stack structure including a gate stack is disposed on the substrate. The source and drain region is disposed beside the stack structure. The sidewall insulator is disposed on the source and drain region. The sidewall insulator includes a bottom portion and an upper portion. An interface is formed between the bottom portion and the upper portion and the bottom portion is located between the upper portion and the source and drain region. The metal connector stacks on the source and drain region and the sidewall insulator is located between the metal connector and the stack structure.

Claims

1. A method of fabricating a Fin-FET device, comprising:

forming a gate stack on a fin of a substrate;

forming a source and drain region beside the gate stack;

forming a preliminary dielectric layer on the substrate over the gate stack and the source and drain region, and the preliminary dielectric layer partially exposing the gate stack, wherein the forming of the preliminary dielectric layer comprises forming a dielectric material layer continuously covering the gate stack and the source and drain region, and patterning the dielectric material layer into the preliminary dielectric layer comprising a first dielectric portion over the source and drain region and a second dielectric portion over the gate stack;

forming an insulation layer to continuously cover the preliminary dielectric layer and an exposed portion of the gate stack;

partially removing the insulation layer and the preliminary dielectric layer until exposing the source and drain region and remaining a portion of the insulation layer and a portion of the preliminary dielectric layer at a sidewall of the gate stack to serve as a sidewall insulator on the source and drain region; and

forming a metal connector on the source and drain region and the metal connector being isolated from the gate stack by the sidewall insulator.

2. The method according to claim 1, wherein the partially removing of the insulation layer and the preliminary dielectric layer further exposes the second dielectric portion to form an interlayer dielectric layer stacking on the gate stack.

3. The method according to claim 1, further comprising performing a planarization process on the metal connector and the sidewall insulator.

4. The method according to claim 3, wherein the planarization process comprises a Chemical-Mechanical Polishing process.

5. The method according to claim 1, further comprising forming a cap layer on the metal connector and the gate stack.

6. A method of fabricating a Fin-FET device, comprising:

forming a gate stack on a fin of a substrate;

forming a source and drain region beside the gate stack;

forming a dielectric material layer continuously covering the gate stack and the source and drain region;

patterning the dielectric material layer into a preliminary dielectric layer comprising a first dielectric portion over the source and drain region and a second dielectric portion over the gate stack, separating the first dielectric portion and the second dielectric portion from each other and exposing a section of a sidewall of the gate stack;

forming an insulation layer to continuously cover the preliminary dielectric layer and the section of the sidewall of the gate stack;

partially removing the insulation layer and the preliminary dielectric layer until exposing the source and drain region and remaining a portion of the first dielectric portion on the source and drain region and a portion of the insulation layer at the section of the sidewall of the gate stack and on the portion of the first dielectric portion to serve as a sidewall insulator on the source and drain region; and

forming a metal connector on the source and drain region and the metal connector being isolated from the gate stack by the sidewall insulator.

7. The method according to claim 6, wherein the partially removing of the insulation layer and the preliminary dielectric layer comprises removing the insulation layer to expose the second dielectric portion to form an interlayer dielectric layer stacking on the gate stack.

8. The method according to claim 6, further comprising performing a planarization process on the metal connector and the sidewall insulator.

9. The method according to claim 8, wherein the planarization process comprises a Chemical-Mechanical Polishing process.

10. The method according to claim 6, further comprising forming a cap layer on the metal connector and the gate stack.

11. A Fin-FET device, comprising:

a substrate having a fin;

a stack structure comprising a gate stack disposed on the fin of the substrate, wherein the gate stack has a sidewall;

a source and drain region beside the gate stack;

metal connectors disposed on the source and drain region; and

a sidewall insulator disposed on the source and drain region and located between the metal connector and the stack structure, wherein the sidewall insulator comprises a first insulator disposed on the source and drain region and a second insulator disposed on a top surface of the first insulator,

wherein the stack structure has an oblique side surface arranged obliquely with respect to the sidewall of the gate stack, the sidewall of the gate stack is between the oblique surface and the fin, and the sidewall insulator covers the stack structure along the sidewall of the gate stack and the oblique side surface to have a turning portion.

12. The Fin-FET device according to claim 11, wherein the stack structure further comprises an interlayer dielectric layer stacking on the gate stack.

13. The Fin-FET device according to claim 12, wherein the interlayer dielectric layer and the first insulator of the sidewall insulator comprise a same material.

14. The Fin-FET device according to claim 12, wherein the sidewall insulator is further located between the metal connector and the interlayer dielectric layer.

15. The Fin-FET device according to claim 12, wherein the gate stack comprises an electrode portion, a spacer covering a sidewall of the electrode portion and a top isolator over a top of the electrode portion, the spacer is located between the electrode portion and the sidewall insulator and between the electrode portion and the source and drain region.

16. The Fin-FET device according to claim 15, wherein the spacer of the gate stack has a taper top portion proximate to the interlayer dielectric layer.

17. The Fin-FET device according to claim 11, wherein the metal connector comprising an expansion portion and a thin portion between the expansion portion and the source and drain region, and an area of the expansion portion exceeds an area of the thin portion.

18. The Fin-FET device according to claim 11, further comprising a cap layer on the metal connector and on the stack structure.