Sacrificial non-epitaxial gate stressors

• US 9,893,187 B2
• Filed: 11/02/2016
• Issued: 02/13/2018
• Est. Priority Date: 05/24/2016
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kittl, Jorge A., Bowen, Chris, Imai, Kiyotaka, Rodder, Mark S.
• Primary Examiner(s): Vu, Vu A
• Application Number:
  US15/342,008
• Publication Number:
  US 20170345932A1
• Time in Patent Office: 468 Days
• Field of Search: 438104
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

Claims

1. A method for fabricating a strained channel for a fin field effect transistor (finFET) device having a fin comprising the channel, the method comprising:

forming, on the fin, a dummy gate to create strain in the channel, a portion of the dummy gate being under a stress of at least 200 megapascals (MPa);

forming a first source drain recess at a first end of the fin;

forming a second source drain recess at a second end of the fin;

forming a first source drain within the first source drain recess;

forming a second source drain within the second source drain recess; and

removing the dummy gate.

2. The method of claim 1, wherein the portion of the dummy gate is under a stress of at least 300 MPa.

3. The method of claim 1, wherein the portion of the dummy gate is under a stress of at least 500 MPa.

4. The method of claim 1, wherein the dummy gate comprises an insulating layer directly on the fin, the insulating layer having a thickness of less than 5 nanometers (nm).

5. The method of claim 4, wherein the insulating layer has a thickness of less than 3 nanometers (nm).

6. The method of claim 4, wherein the insulating layer comprises, as a major component, an oxide.

7. The method of claim 1, wherein the forming of the dummy gate comprises:

forming an insulating layer, of a first material, having a thickness of less than 5 nm, directly on the fin; and

forming a layer of a second material directly on the insulating layer, the second material being capable of developing a compressive or tensile stress in response to a process selected from the group consisting of ion implantation, plasma doping, annealing, and combinations thereof.

8. The method of claim 1, wherein the fin has a thickness less than about 8 nm.

9. The method of claim 1, wherein:

the forming of the first source drain recess comprises forming the first source drain recess to a depth of at least about 10 nm; and

the forming of the second source drain recess comprises forming the second source drain recess to a depth of at least about 10 nm.

10. The method of claim 1, wherein:

the forming of the first source drain comprises growing the first source drain as an epitaxial layer; and

the forming of the second source drain comprises growing the second source drain as an epitaxial layer,

a strain state in the channel after the forming of the first source drain and the forming of the second source drain having a strain greater, by at least 10%, than a strain of the strain state in the channel before the forming of the first source drain and the forming of the second source drain.

11. The method of claim 1, wherein:

the forming of the first source drain comprises growing the first source drain as an epitaxial layer; and

the forming of the second source drain comprises growing the second source drain as an epitaxial layer,

a strain state in the channel after the forming of the first source drain and the forming of the second source drain having a strain differing from a strain of the strain state in the channel before the forming of the first source drain and the forming of the second source drain by no more than 30%.

12. The method of claim 11, wherein the strain of the strain state in the channel after the forming of the first source drain and the forming of the second source drain differs from the strain of the strain state in the channel before the forming of the first source drain and the forming of the second source drain by no more than 10%.

13. The method of claim 1, wherein the finFET device is an n-type metal oxide semiconductor device.

14. The method of claim 1, wherein the finFET device is a p-type metal oxide semiconductor device.

15. The method of claim 14, wherein the first source drain is composed of:

silicon, or

silicon germanium including at least 30% germanium.

16. A method for fabricating a strained channel for a fin field effect transistor (finFET) device having a fin comprising the channel, the method comprising:

forming, on the fin, a dummy gate, a portion of the dummy gate being under a stress of at least 200 megapascals (MPa);

forming a first source drain recess at a first end of the fin;

forming a second source drain recess at a second end of the fin;

forming a first source drain within the first source drain recess;

forming a second source drain within the second source drain recess; and

removing the dummy gate,

wherein;

the forming of the first source drain comprises growing the first source drain as a non-epitaxial layer; and

the forming of the second source drain comprises growing the second source drain as a non-epitaxial layer,

a strain state in the channel after the forming of the first source drain and the forming of the second source drain having a strain differing from a strain of the strain state in the channel before the forming of the first source drain and the forming of the second source drain by no more than 30%.

17. The method of claim 16, wherein the strain of the strain state in the channel after the forming of the first source drain and the forming of the second source drain differs from the strain of the strain state in the channel before the forming of the first source drain and the forming of the second source drain by no more than 10%.

18. A method for fabricating a strained channel for a fin field effect transistor (finFET) device having a fin comprising the channel, the method comprising:

forming, on the fin, a dummy gate;

forming a first source drain recess at a first end of the fin;

forming a second source drain recess at a second end of the fin;

forming a first source drain within the first source drain recess;

forming a second source drain within the second source drain recess; and

removing the dummy gate;

the forming of the dummy gate comprising;

forming a first layer, of a first material, having a thickness of less than 5 nm, directly on the fin;

forming a second layer, of a second material, directly on the first layer;

incorporating one or more additional elements into the second layer; and

annealing the second layer at a temperature of at least 700 C and at most 1000 C,

the incorporating of the one or more additional elements comprising utilizing a process selected from the group consisting of plasma doping, ion implantation, and combinations thereof,

the additional elements being selected from arsenic, phosphorus, and combinations thereof,

the incorporating of the one or more additional elements comprising incorporating one or more additional elements at a total dose of at least 1e15 cm<sup>−

2</sup> and at most 5e16 cm<sup>−

2</sup>, and

the incorporating of the one or more additional elements into the second layer resulting in sufficiently little incorporating of the one or more additional elements into the fin to avoid affecting electrical characteristics of the finFET device.

19. The method of claim 18, wherein the incorporating of the one or more additional elements comprising incorporating one or more additional elements at a total dose of about 1e15 cm⁻

2, and the annealing of the second layer comprises annealing of the second layer at a temperature of about 900 C.

20. A method for straining a fin of a fin field effect transistor (FinFET) device, the fin being substantially a single crystal, the method comprising:

forming, on the fin, a dummy gate;

forming a first source drain recess at a first end of the fin;

forming a second source drain recess at a second end of the fin;

forming a first source drain within the first source drain recess;

forming a second source drain within the second source drain recess;

removing the dummy gate; and

forming a replacement metal gate,

the forming of the dummy gate comprising;

forming a first layer, of a first material, having a thickness of less than 5 nm, directly on the fin;

forming a second layer, of a second material, directly on the first layer;

incorporating one or more additional elements into the second layer; and

forming a third layer directly on the second layer,

a total height of the first layer, the second layer, and the third layer being substantially the same as a total height of the replacement metal gate.