Method of forming a wire bond sensor package

• US 9,893,213 B2
• Filed: 04/20/2017
• Issued: 02/13/2018
• Est. Priority Date: 08/18/2014
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage, Lu, Zhenhua
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US15/492,592
• Publication Number:
  US 20170222065A1
• Time in Patent Office: 299 Days
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10155 being other than a cuboid
• CPC Class Codes: H01L 2924/10156 at the periphery
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A packaged chip assembly with a semiconductor substrate, a semiconductor device integrally formed on or in the substrate'"'"'s top surface, and first bond pads at the substrate'"'"'s top surface electrically coupled to the semiconductor device. A second substrate includes a first aperture and one or more second apertures extending therethrough, second and third bond pads at the second substrate'"'"'s top and bottom surfaces, respectively, and conductors electrically coupled to the second and third bond pads. The semiconductor substrate'"'"'s top surface is secured to the second substrate'"'"'s bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the second apertures. A plurality of wires are each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.

Claims

1. A method of forming a packaged chip assembly, comprising:

providing a semiconductor chip that includes;

a first substrate of semiconductor material having first top and first bottom surfaces,

a semiconductor device integrally formed on or in the first top surface, and

first bond pads at the first top surface electrically coupled to the semiconductor device;

providing a second substrate that includes;

second top and second bottom surfaces,

a first aperture extending between the second top and second bottom surfaces,

one or more second apertures extending between the second top and second bottom surfaces,

second bond pads at the second top surface,

third bond pads at the second bottom surface, and

conductors electrically coupled to the second bond pads and the third bond pads;

securing the first top surface to the second bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the one or more second apertures; and

electrically connecting each of a plurality of wires between one of the first bond pads and one of the second bond pads, wherein each of the plurality of wires passes through one of the one or more second apertures.

2. The method of claim 1, further comprising:

securing a third substrate to the second top surface, wherein the third substrate covers the first aperture and is optically transparent or semitransparent, and wherein the semiconductor device is one of an image sensor, an infrared sensor, and a light sensor.

3. The method of claim 1, further comprising:

covering the wires with, and filling the one or more second apertures with, encapsulant.

4. The method of claim 1, further comprising:

providing a third substrate that includes;

third top and third bottom surfaces, and

fourth bond pads at the third top surface; and

securing the third top surface to the second bottom surface using electrical interconnects that are each electrically coupling one of the third bond pads to one of the fourth bond pads.

5. A method of forming a packaged chip assembly, comprising:

providing a semiconductor chip that includes;

a first substrate of semiconductor material having first top and first bottom surfaces,

a semiconductor device integrally formed on or in the first top surface, and

first bond pads at the first top surface electrically coupled to the semiconductor device;

forming one or more trenches into the first top surface;

forming a plurality of conductive traces each having a first portion electrically connected to one of the first bond pads, a second portion extending over and insulated from the first top surface, and a third portion extending down into one of the one or more trenches;

providing a second substrate that includes;

second top and second bottom surfaces,

second bond pads at the second top surface,

third bond pads at the second bottom surface, and

conductors electrically coupled to the second bond pads and to the third bond pads;

securing the first bottom surface to the second top surface;

electrically connecting each of a plurality of wires between one of the third portions of one of the plurality of conductive traces and one of the second bond pads;

providing a third substrate that includes;

third top and third bottom surfaces, and

fourth bond pads at the third top surface; and

securing the third top surface to the second bottom surface using electrical interconnects that are each electrically coupling one of the third bond pads to one of the fourth bond pads.

6. The method of claim 5, further comprising:

securing a fourth substrate to the first top surface, wherein the fourth substrate is disposed over the semiconductor device.

7. The method of claim 6, wherein the fourth substrate comprises multiple sheets of single crystal sapphire layered in different crystal plane orientations.

8. The method of claim 5, further comprising:

covering the wires and the conductive traces with encapsulant.