High quality factor interconnect for RF circuits

• US 9,893,710 B2
• Filed: 06/06/2014
• Issued: 02/13/2018
• Est. Priority Date: 06/06/2013
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Leipold, Dirk Robert Walter, Scott, Baker, Maxim, George
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US14/298,834
• Publication Number:
  US 20140361856A1
• Time in Patent Office: 1,348 Days
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/267 A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03H 2210/012 Centre frequency; Cut-off frequency
• CPC Class Codes: H03H 2210/025 Capacitor
• CPC Class Codes: H03H 2210/04 Filter calibration method
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/09 Filters comprising mutual inductance
• CPC Class Codes: H03H 7/1775 Parallel LC in shunt or branch path H03H7/1791 takes precedence
• CPC Class Codes: H03H 7/46 Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source for use in multiplex transmission systems H04J1/00
• CPC Class Codes: H03H 7/463 Duplexers
• CPC Class Codes: H03H 7/465 having variable circuit topology, e.g. including switches
• CPC Class Codes: H04B 1/1027 : assessing signal quality or detecting noise/interference for the received signal
• CPC Class Codes: H04B 1/18 : Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H

Abstract

Embodiments of radio frequency (RF) devices are disclosed having interconnection paths with capacitive structures having improved quality (Q) factors. In one embodiment, an RF device includes an inductor having an inductor terminal and a semiconductor die. The semiconductor die includes one or more active semiconductor devices that include a device contact. The device contact provided by the one or more active semiconductor devices is positioned so as to be vertically aligned directly below the inductor terminal. The inductor terminal and the device contact are electrically connected with an interconnection path that includes a capacitive structure. To prevent or reduce current crowding, the interconnection path is vertically aligned so as to extend directly between the inductor terminal and the device contact. In this manner, the interconnection path electrically connects the inductor terminal and the device contact without degrading the Q factor of the RF device.

Claims

1. A radio frequency (RF) device, comprising:

an inductor having a first inductor terminal; and

a semiconductor die comprising;

one or more field effect transistors having device contacts that include a first device contact, wherein the first device contact of one of the one or more field effect transistors is either a source contact or a drain contact, wherein the first device contact is vertically aligned so as to be positioned directly below the first inductor terminal;

a first interconnection path that electrically connects the first inductor terminal to the first device contact, wherein the first interconnection path is vertically aligned so as to extend directly between the first inductor terminal and the first device contact; and

a first capacitive structure that is formed within the first interconnection path wherein the first capacitive structure is vertically aligned so as to be positioned directly over the first device contact and directly underneath the first inductor terminal.

2. The RF device of claim 1, wherein the semiconductor die comprises a semiconductor substrate and a Back End of Line (BEOL) formed over the semiconductor substrate, wherein:

the one or more field effect transistors are formed by the semiconductor substrate; and

the first capacitive structure is formed by the BEOL.

3. The RF device of claim 1, wherein the semiconductor die comprises a semiconductor substrate and a Back End of Line (BEOL) formed over the semiconductor substrate, wherein:

the one or more field effect transistors are formed by the semiconductor substrate; and

the first interconnection path is formed by the BEOL.

4. The RF device of claim 1 further comprising a package board wherein:

the inductor is formed by the package board; and

the semiconductor die is attached to the package board.

5. The RF device of claim 4, wherein the package board comprises a laminate having a laminate surface and a metallic layer formed on the laminate surface, wherein the metallic layer forms the first inductor terminal.

6. The RF device of claim 5 wherein the metallic layer forms all of the inductor.

7. The RF device of claim 1 wherein:

the inductor further comprises a second inductor terminal;

one or more active semiconductor devices further includes a second device contact, the second device contact being vertically aligned so as to be positioned directly below the second inductor terminal; and

the semiconductor die further comprises a second interconnection path and a second capacitive structure, wherein;

the second interconnection path electrically connects the second inductor terminal to the second device contact, the second interconnection path being vertically aligned so as to extend directly between the second inductor terminal and the second device contact; and

the second capacitive structure is formed in the second interconnection path.

8. The RF device of claim 7 wherein the one or more active semiconductor devices electrically connect the first device contact to the second device contact.

9. The RF device of claim 7 wherein the one or more active semiconductor devices provide a switch path that electrically connects the first interconnection path to the second interconnection path so that the first interconnection path, the switch path, and the second interconnection path provide a current path between the first inductor terminal and the second inductor terminal.

10. The RF device of claim 9 wherein the one or more active semiconductor devices are configured to:

open the current path when the one or more active semiconductor devices are turned on; and

close the current path when the one or more active semiconductor devices are turned off.

11. The RF device of claim 7 wherein the semiconductor die comprises a semiconductor substrate and a Back End of Line (BEOL) formed over the semiconductor substrate, wherein:

the one or more active semiconductor devices are formed by the semiconductor substrate;

the first interconnection path is formed by the BEOL; and

the second interconnection path is formed by the BEOL.

12. The RF device of claim 7 wherein a first horizontal displacement between the first inductor terminal and the second inductor terminal is substantially equal to a second horizontal displacement between the first device contact and the second device contact.

13. The RF device of claim 12 wherein the one or more active semiconductor devices are positioned horizontally directly between the first interconnection path and the second interconnection path.

14. The RF device of claim 1 wherein:

the first interconnection path has a path width; and

the first inductor terminal has a terminal width;

wherein the path width and the terminal width are substantially equal.

15. The RF device of claim 1 wherein:

the first inductor terminal has a first inductor terminal connection surface that is attached to the first interconnection path;

the first device contact has a first device contact connection surface; and

the first interconnection path is formed to extend vertically such that the first interconnection path is substantially orthogonal to both the first inductor terminal connection surface and the first device contact connection surface.

16. The RF device of claim 15 wherein all of the first interconnection path is aligned directly between the first inductor terminal connection surface and the first device contact connection surface.

17. The RF device of claim 1 wherein:

the first inductor terminal has a first inductor terminal connection surface that is attached to the first interconnection path;

the first device contact has a first device contact connection surface; and

the first interconnection path is formed to extend vertically such that the first interconnection path is aligned directly between the first inductor terminal connection surface and the first device contact connection surface.

18. The RF device of claim 1 wherein the first interconnection path extends directly between the first inductor terminal and the first device contact such that a current has a first direction of current flow through the first interconnection path that is substantially orthogonal to a second direction of current flow of the current through the first inductor terminal.

19. The RF device of claim 18 wherein the first interconnection path extends directly between the first inductor terminal and the first device contact such that the first direction of current flow through the first interconnection path is also substantially orthogonal to a third direction of current flow of the current through the one or more field effect transistors.

20. The RF device of claim 1 wherein the first capacitive structure has an array of traces configured to split a current propagating within the first interconnection path.

21. The RF device of claim 1 wherein the inductor is selected from a group consisting of a horizontal inductor, a vertical inductor, and a three-dimensional inductor.

22. The RF device of claim 1 wherein the first capacitive structure is a metal-insulator-metal (MIM) capacitive structure.

23. The RF device of claim 1 wherein the first capacitive structure is a metal-oxide-metal (MOM) capacitive structure.

24. The RF device of claim 1 wherein the first capacitive structure is a metal-to-metal (MTM) capacitive structure.

25. The RF device of claim 24 wherein the MTM capacitive structure comprises parallel metallic walls formed across the one or more of the device contacts including the first device contact.

26. The RF device of claim 24 wherein the MTM capacitive structure comprises alternating metallic posts encircled by metallic cages.

27. The RF device of claim 1 wherein the one or more field effect transistors comprise a stack of field effect transistors.

29. The RF device of claim 1 wherein the first capacitive structure is directly provided on the first device contact.

28. An integrated circuit (IC) package comprising:

a package board;

an inductor formed by the package board, wherein the inductor has a first inductor terminal; and

a semiconductor die comprising a semiconductor substrate and a Back-End-of-Line (BEOL) formed over the semiconductor substrate, wherein;

the semiconductor substrate comprises one or more field effect transistors having device contacts that include a first device contact, wherein the first device contact of one of the one or more field effect transistors is either a source contact or a drain contact, wherein the first device contact is vertically aligned so as to be positioned directly below the first inductor terminal; and

the BEOL comprises;

a first interconnection path that electrically connects the first inductor terminal to the first device contact, wherein the first interconnection path is vertically aligned so as to extend directly between the first inductor terminal and the first device contact; and

a first capacitive structure that is formed within the interconnection path wherein the first capacitive structure is vertically aligned so as to be positioned directly over the first device contact and directly underneath the first inductor terminal.

30. The IC package of claim 28 wherein the first capacitive structure is directly provided on the first device contact.