Technique for crosstalk reduction

• US 9,893,913 B2
• Filed: 10/26/2016
• Issued: 02/13/2018
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Mu, Fenghao, Sundstrm, Lars
• Primary Examiner(s): LAM, KENNETH T
• Application Number:
  US15/334,970
• Publication Number:
  US 20170048089A1
• Time in Patent Office: 475 Days
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

Abstract

A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.

Claims

1. An arrangement for reducing crosstalk between a first controlled oscillator and a second controlled oscillator, the arrangement comprising:

a first crosstalk detector adapted to detect a crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);

a first crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal; and

a first cancellation signal injector adapted to introduce the cancellation signal into the second CO, wherein

the first crosstalk detector comprises;

a mixer stage adapted to produce a mixed signal (m1(t)) by mixing a clock signal (S1(t)) generated by the second CO with a signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;

a filter adapted to filter the mixed signal (m1(t)) to produce a filtered signal;

a signal converter adapted to down-convert the filtered signal into a DC signal (m2(t)); and

an output for outputting the DC (m2(t)) signal as an indication for the crosstalk signal.

2. The arrangement of claim 1, wherein the first controlled oscillator and the second controlled oscillator are integrated one chip.

3. The arrangement of claim 1, further comprising:

a controller adapted to provide a control signal to adjust at least one or more of the amplitude of the cancellation signal and the phase of the cancellation signal based on the indication for the crosstalk signal.

4. The arrangement of claim 1, wherein the first crosstalk cancellation circuit further comprises at least one of:

a variable gain amplifier adapted to adjust the amplitude of the cancellation signal; and

a variable phase shift circuit adapted to adjust the phase of the cancellation signal.

5. The arrangement of claim 1, wherein

the first crosstalk cancellation circuit further comprises an adjustment circuitry adapted to adjust the cancellation signal, the adjustment circuitry comprising a quadrature phase splitter arranged to provide a first cancellation signal component with a first phase shift and provide a second cancellation signal component with a second phase shift, where the difference between the second and the first phase shifts is essentially 90 degrees, and

the adjustment circuitry further comprises at least one of:

a first variable gain amplifier adapted to adjust an amplitude of the first cancellation signal component; and

a second variable gain amplifier adapted to adjust an amplitude of the second cancellation signal component, wherein the first crosstalk cancellation circuit is adapted to generate the cancellation signal as a sum of the first and second cancellation signal components with any amplitude adjustments.

6. The arrangement of claim 1, wherein the signal converter comprises one of a rectifier and a component comprising a low pass filter (LPF) and an amplifier (Ampb) adapted to extract a magnitude of the filtered signal.

7. The arrangement of claim 1, wherein the first cancellation signal injector further comprises a buffer adapted to isolate the cancellation signal from the second CO.

8. The arrangement of claim 1, wherein the first cancellation signal injector comprises a coupler for coupling the cancellation signal to the second CO, wherein the coupler is adapted to provide one of an inductive coupling and a capacitive coupling.

9. The arrangement of claim 8, further comprising on-chip twisted differential transmission lines between the first CO and the second CO.

10. The arrangement of claim 1, further comprising:

a second crosstalk detector adapted to detect another crosstalk signal generated by the second CO to the first CO;

a second crosstalk cancellation circuit adapted to generate another cancellation signal having an amplitude substantially the same as that of the crosstalk signal detected by the second crosstalk detector and a phase substantially opposite to that of the crosstalk signal detected by the second crosstalk detector; and

a second cancellation signal injector adapted to introduce the other cancellation signal into the first CO.

11. A radio communication device, comprising:

an integrated circuit having a first controlled oscillator and a second controlled oscillator; and

an arrangement for reducing a crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, the arrangement comprising;

a first crosstalk detector adapted to detect the crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);

a first crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal; and

a first cancellation signal injector adapted to introduce the cancellation signal into the second CO, wherein

the first crosstalk detector comprises;

a mixer stage adapted to produce a mixed signal (m1(t)) by mixing a clock signal (S1(t)) generated by the second CO with a signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;

a filter adapted to filter the mixed signal (m1(t)) to produce a filtered signal;

a signal converter adapted to down-convert the filtered signal into a DC signal (m2(t)); and

an output for outputting the DC signal as an indication for the crosstalk signal.

12. A method of reducing a crosstalk signal generated by a first controlled oscillator to a second controlled oscillator both comprised in an integrated circuit, the method being performed by an electronic device and comprising the steps of:

the electronic device detecting a crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);

the electronic device generating a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal;

the electronic device injecting the cancellation signal into the second CO to reduce the crosstalk signal;

the electronic device producing a mixed signal (m1(t)) by mixing a clock signal (S1(t)) generated by the second CO with a signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;

the electronic device filtering the mixed signal (m1(t)) to produce a filtered signal;

the electronic device down-converting the filtered signal into a DC signal (m2(t)); and

the electronic device outputting the DC signal as an indication for the crosstalk signal.

13. The method of claim 12, further comprising:

the electronic device controlling at least one or more of the amplitude and the phase of the cancellation signal based on the indication for the crosstalk signal.

14. A method of reducing a crosstalk signal generated by a first controlled oscillator to a second controlled oscillator both comprised in an integrated circuit, each of the controlled oscillators adapted to output a respective clock signal, the method being performed by an electronic device and comprising the steps of:

the electronic device detecting a first crosstalk signal generated by the first controlled oscillator (CO);

the electronic device generating a first cancellation signal having an amplitude substantially the same as that of the first crosstalk signal and a phase substantially opposite to that of the first crosstalk signal;

the electronic device injecting the first cancellation signal into the second CO;

the electronic device detecting a second crosstalk signal generated by the second CO to the first CO;

the electronic device generating a second cancellation signal having an amplitude substantially the same as that of the second crosstalk signal and a phase substantially opposite to that of the second crosstalk signal; and

the electronic device injecting the second cancellation signal into the first CO.