Techniques for packet management in an input/output virtualization system

• US 9,893,996 B2
• Filed: 01/04/2016
• Issued: 02/13/2018
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dong, Yao Z
• Primary Examiner(s): MEW, KEVIN D
• Application Number:
  US14/987,634
• Publication Number:
  US 20160359743A1
• Time in Patent Office: 771 Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 2213/0058 Bus-related hardware virtualisation
• CPC Class Codes: H04L 45/586 of virtual routers
• CPC Class Codes: H04L 45/741 Routing in networks with a plurality of addressing schemes, e.g. with both IPv4 and IPv6
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/70 Virtual switches

Abstract

Embodiments include techniques for managing packets in an input/output virtualization (IOV) capable computing environment. Embodiments include determining a destination address of a packet received at a virtual router, modifying the destination address of the packet to correspond with a destination within an input/output (I/O) virtualization capable adapter; and forwarding the packet to an I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

Claims

1. An apparatus comprising:

a processing circuit; and

a memory storing instructions operable on the processing circuit, the instructions, when executed, cause the processing circuit to;

determine a destination address of a packet received at a virtual router;

modify the destination address of the packet to correspond with a destination within an input/output (I/O) virtualization capable adapter; and

forward the packet to an I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

2. The apparatus of claim 1, the packet comprising an Internet Protocol (IP) address and a first media access control (MAC) address.

3. The apparatus of claim 2, the processing circuit to determine a virtual function associated with the IP address, the I/O virtualization capable adapter comprising the virtual function.

4. The apparatus of claim 3, the processing circuit to determine a second MAC address as the destination address based on the IP address, the second MAC address associated with the virtual function.

5. The apparatus of claim 2, the first MAC address associated with a proxy interface upstream component, and the processing circuit to change the first MAC address to a second MAC address associated with a virtual function.

6. The apparatus of claim 1, the I/O virtualization capable adapter to include a proxy interface downstream component, the proxy interface downstream component to forward the packet to the I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

7. The apparatus of claim 6, the proxy interface downstream component to forward the packet to a layer 2 switch within the I/O virtualization capable adapter architecture.

8. The apparatus of claim 1, the I/O virtualization capable adapter architecture to transmit the packet to the destination within the I/O virtualization capable adapter in accordance with a single root I/O virtualization process.

9. The apparatus of claim 1, comprising a transceiver coupled with the processing circuit and the memory, the transceiver to communicate the packet.

10. One or more non-transitory computer-readable media to store instructions that when executed by a processor circuit causes the processor circuit to:

determine a destination address of a packet received at a virtual router;

modify the destination address of the packet to correspond with a destination within an input/output (I/O) virtualization capable adapter; and

forward the packet to an I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

11. The non-transitory one or more computer-readable media of claim 10, the packet comprising an Internet Protocol (IP) address and a first media access control (MAC) address.

12. The non-transitory one or more computer-readable media of claim 11, with instructions to determine a virtual function associated with the IP address, the I/O virtualization capable adapter comprising the virtual function.

13. The non-transitory one or more computer-readable media of claim 12, with instructions to determine a second MAC address as the destination address based on the IP address, the second MAC address associated with the virtual function.

14. The non-transitory one or more computer-readable media of claim 11, the first MAC address associated with a proxy interface upstream component, and with instructions to change the first MAC address to a second MAC address associated with a virtual function.

15. The non-transitory one or more computer-readable media of claim 10, the I/O virtualization capable adapter to include a proxy interface downstream component, the proxy interface downstream component to forward the packet to the I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

16. The non-transitory one or more computer-readable media of claim 15, the proxy interface downstream component to forward the packet to a layer 2 switch within the I/O virtualization capable adapter architecture.

17. The non-transitory one or more computer-readable media of claim 10, the I/O virtualization capable adapter architecture to transmit the packet to the destination within the I/O virtualization capable adapter in accordance with a single root I/O virtualization process.

18. The non-transitory one or more computer-readable media of claim 10, comprising a transceiver coupled with the processing circuitry and the memory, the transceiver to communicate the packet.

19. A computer-implemented method, comprising:

determining a destination address of a packet received at a virtual router;

modifying the destination address of the packet to correspond with a destination within an input/output (I/O) virtualization capable adapter; and

forwarding the packet to an I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

20. The computer-implemented method of claim 19, the packet comprising an Internet Protocol (IP) address and a first media access control (MAC) address.

21. The computer-implemented method of claim 20, comprising determining a virtual function associated with the IP address, the I/O virtualization capable adapter comprising the virtual function.

22. The computer-implemented method of claim 21, comprising determining a second MAC address as the destination address based on the IP address, the second MAC address associated with the virtual function.

23. The computer-implemented method of claim 20, the first MAC address associated with a proxy interface upstream component, and comprising changing the first MAC address to a second MAC address associated with a virtual function.

24. The computer-implemented method of claim 19, the I/O virtualization capable adapter including a proxy interface downstream component, the proxy interface downstream component to forward the packet to the I/O virtualization capable adapter architecture for transmission to the destination within the I/O virtualization capable adapter.

25. The computer-implemented method of claim 24, the proxy interface downstream component to forward the packet to a layer 2 switch within the I/O virtualization capable adapter architecture.