Method for testing comparator and device therefor

• US 9,897,649 B2
• Filed: 09/14/2015
• Issued: 02/20/2018
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Ren, Juxiang, Dao, Chris C., Pietri, Stefano
• Primary Examiner(s): Hoque, Farhana
• Application Number:
  US14/853,090
• Publication Number:
  US 20160003908A1
• Time in Patent Office: 890 Days
• Field of Search: 324252, 32475003, 327 73
• CPC Class Codes: G01R 31/3163 Functional testing
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Claims

1. A device comprising:

a comparator comprising a first comparator input, a second comparator input, and a comparator output;

a selection circuit comprising a first data input, a second data input, a select input and an output coupled to the first input of the comparator, the first input to receive a first voltage identifying a first extreme voltage of an operational voltage range, the second input coupled to receive a second voltage, the first extreme voltage between the first voltage and a second extreme voltage of the operational voltage range; and

a delay path between the output of the comparator and the select input of the selection circuit that asynchronously selects the first data input of the selection circuit responsive to the second input being previously selected.

2. The device of claim 1 wherein the asynchronous delay path comprises:

control logic having a first input to receive a self-test indicator, a second input to receive a signal communicated from the output of the comparator, and an output to provide a first select signal to switch from selecting the first input to selecting the second data input of the selection circuit in response to receiving an asserted self-test indicator at the first input, and to asynchronously provide a second select signal to switch from selecting the second data input to selecting the first data input of the selection circuit in response to the comparator providing a signal that indicates the first voltage reference is outside the operational voltage range.

3. The device of claim 1 further comprising:

a first programmable location to store a first indicator; and

a control logic that comprises the delay path having a first input coupled to the first programmable storage location, a second input coupled to the output of the comparator, and an output to provide a select signal to select the second data input of the selection circuit responsive to a state of the first indicator, and to subsequently provide the select signal to select the first input responsive to a change of state at the output of the comparator occurring responsive to providing the second reference voltage to the comparator.

4. The device of claim 1, wherein the delay path includes self-test control logic to verify proper operation of the comparator in response to the second input being selected.

5. The device of claim 4, wherein the self-test control logic is to periodically verify proper operation of the comparator in response to a first programmable location storing a first indicator.

6. The device of claim 1, wherein the self-test control logic is to verify proper operation of the comparator only one time in response to a first programmable location storing a first indicator.