Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data

• US 9,898,212 B1
• Filed: 01/06/2017
• Issued: 02/20/2018
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Primary Examiner(s): Nguyen, Hiep
• Application Number:
  US15/400,154
• Time in Patent Office: 410 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A method of programming a memory having at least a first memory block and a second block, the method comprising:

assigning (i) a first weighting factor to the first memory block and (ii) a second weighting factor to the second memory block, the first weighting factor being different from the second weighting factor;

tracking (i) a first number of write-erase cycles that the first memory block undergoes and (ii) a second number of write-erase cycles that the second memory block undergoes;

receiving data to be written to the memory;

based on (i) the first weighting factor assigned to the first memory block, (ii) the second weighting factor assigned to the second memory block, (iii) the first number of write-erase cycles that the first memory block undergoes, and (iv) the second number of write-erase cycles that the second memory block undergoes, selecting one of the first memory block or the second memory block; and

writing the data to the selected one of the first memory block or the second memory block.

2. The method of claim 1, wherein selecting one of the first memory block or the second memory block comprises:

based on (i) the first weighting factor assigned to the first memory block and (ii) the first number of write-erase cycles that the first memory block undergoes, determining a first weighted number of write-erase cycles for the first memory block;

based on (i) the second weighting factor assigned to the second memory block and (ii) the second number of write-erase cycles that the second memory block undergoes, determining a second weighted number of write-erase cycles for the second memory block; and

based on (i) the first weighted number of write-erase cycles for the first memory block and (ii) the second weighted number of write-erase cycles for the second memory block, selecting one of the first memory block or the second memory block.

3. The method of claim 1, wherein selecting one of the first memory block or the second memory block further comprises:

determining that the first weighted number of write-erase cycles for the first memory block is less than the second weighted number of write-erase cycles for the second memory block; and

based on determining that the first weighted number of write-erase cycles for the first memory block is less than the second weighted number of write-erase cycles for the second memory block, selecting the first memory block.

4. The method of claim 1, wherein determining the first weighted number of write-erase cycles for the first memory block comprises:

determining the first weighted number of write-erase cycles for the first memory block to be based on a multiple of (i) the first weighting factor assigned to the first memory block and (ii) the first number of write-erase cycles that the first memory block undergoes.

5. The method of claim 1, wherein the first memory block is configured to withstand higher number of write-erase cycles compared to the second memory block, and wherein assigning the first weighting factor and the second weighting factor comprises:

in response to the first memory block being configured to withstand higher number of write-erase cycles compared to the second memory block, assigning the first weighting factor and the second weighting factor such that the first weighting factor is less than the second weighting factor.

6. The method of claim 1, wherein:

the first memory block is a single-level cell (SLC) memory block;

the second memory block is a multi-level cell (MLC) memory block; and

the first weighting factor is less than the second weighting factor.

7. The method of claim 1, wherein:

the first memory block is of a first type;

the second memory block is of a second type;

memory blocks of the first type, on average, withstand higher number of write-erase cycles than memory blocks of the second type, on average, withstand; and

assigning the first weighting factor and the second weighting factor comprises;

in response to the memory blocks of the first type, on average, withstanding higher number of write-erase cycles than memory blocks of the second type, assigning the first weighting factor and the second weighting factor such that the first weighting factor is less than the second weighting factor.

8. The method of claim 1, wherein:

the memory comprises a first plurality of memory blocks and a second plurality of memory blocks, the first plurality of memory blocks including the first memory bock, and the second plurality of memory blocks including the second memory bock;

each of the first plurality of memory blocks is of a first type;

each of the second plurality of memory blocks is of a second type, the second type being different from the first type; and

the method further comprises;

assigning, to each memory block of the first plurality of memory blocks, the first weighting factor,

assigning, to each memory block of the second plurality of memory blocks, the second weighting factor,

based on the first weighting factor and the second weighting factor, selecting a third memory block from the first and second plurality of memory blocks for writing additional data, and

writing the additional data in the third memory block.

9. The method of claim 8, wherein:

each memory block of the first plurality of memory blocks is a single-level cell (SLC) memory block;

each memory block of the second plurality of memory blocks is a multi-level cell (MLC) memory block; and

the first weighting factor is less than the second weighting factor.

10. The method of claim 1, wherein the memory is a flash memory.

11. A memory system comprising:

a memory comprising a first memory block and a second block; and

a memory controller configured to;

assign (i) a first weighting factor to the first memory block and (ii) a second weighting factor to the second memory block, the first weighting factor being different from the second weighting factor,

track (i) a first number of write-erase cycles that the first memory block undergoes and (ii) a second number of write-erase cycles that the second memory block undergoes,

based on (i) the first weighting factor assigned to the first memory block, (ii) the second weighting factor assigned to the second memory block, (iii) the first number of write-erase cycles that the first memory block undergoes, and (iv) the second number of write-erase cycles that the second memory block undergoes, select one of the first memory block or the second memory block, and

facilitate writing data to the selected one of the first memory block or the second memory block.

12. The memory system of claim 11, wherein the memory controller is configured to select one of the first memory block or the second memory block by:

based on (i) the first weighting factor assigned to the first memory block and (ii) the first number of write-erase cycles that the first memory block undergoes, determining a first weighted number of write-erase cycles for the first memory block;

based on (i) the second weighting factor assigned to the second memory block and (ii) the second number of write-erase cycles that the second memory block undergoes, determining a second weighted number of write-erase cycles for the second memory block; and

based on (i) the first weighted number of write-erase cycles for the first memory block and (ii) the second weighted number of write-erase cycles for the second memory block, selecting one of the first memory block or the second memory block.

13. The memory system of claim 11, wherein the memory controller is further configured to select one of the first memory block or the second memory block by:

determining that the first weighted number of write-erase cycles for the first memory block is less than the second weighted number of write-erase cycles for the second memory block; and

based on determining that the first weighted number of write-erase cycles for the first memory block is less than the second weighted number of write-erase cycles for the second memory block, selecting the first memory block.

14. The memory system of claim 11, wherein the memory controller is configured to determine the first weighted number of write-erase cycles for the first memory block by:

determining the first weighted number of write-erase cycles for the first memory block to be based on a multiple of (i) the first weighting factor assigned to the first memory block and (ii) the first number of write-erase cycles that the first memory block undergoes.

15. The memory system of claim 11, wherein the first memory block is configured to withstand higher number of write-erase cycles compared to the second memory block, and wherein the memory controller is configured to assign the first weighting factor and the second weighting factor by:

in response to the first memory block being configured to withstand higher number of write-erase cycles compared to the second memory block, assigning the first weighting factor and the second weighting factor such that the first weighting factor is less than the second weighting factor.

16. The memory system of claim 11, wherein:

the first memory block is a single-level cell (SLC) memory block;

the second memory block is a multi-level cell (MLC) memory block; and

the first weighting factor is less than the second weighting factor.

17. The memory system of claim 11, wherein:

the first memory block is of a first type;

the second memory block is of a second type;

memory blocks of the first type, on average, withstand higher number of write-erase cycles than memory blocks of the second type, on average, withstand; and

the memory controller is configured to assign the first weighting factor and the second weighting factor by;

in response to the memory blocks of the first type, on average, withstanding higher number of write-erase cycles than memory blocks of the second type, assigning the first weighting factor and the second weighting factor such that the first weighting factor is less than the second weighting factor.

18. The memory system of claim 11, wherein:

the memory comprises a first plurality of memory blocks and a second plurality of memory blocks, the first plurality of memory blocks including the first memory bock, and the second plurality of memory blocks including the second memory bock;

each of the first plurality of memory blocks is of a first type;

each of the second plurality of memory blocks is of a second type, the second type being different from the first type; and

the memory controller is further configured to;

assign, to each memory block of the first plurality of memory blocks, the first weighting factor,

assign, to each memory block of the second plurality of memory blocks, the second weighting factor,

based on the first weighting factor and the second weighting factor, select a third memory block from the first and second plurality of memory blocks for writing additional data, and

facilitate writing the additional data in the third memory block.

19. The memory system of claim 18, wherein:

each memory block of the first plurality of memory blocks is a single-level cell (SLC) memory block;

each memory block of the second plurality of memory blocks is a multi-level cell (MLC) memory block; and

the first weighting factor is less than the second weighting factor.

20. The memory system of claim 11, wherein the memory is a flash memory.