Resource sharing in a telecommunications environment

• US 9,898,220 B2
• Filed: 12/08/2016
• Issued: 02/20/2018
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: TQ Delta LLC (Techquity Capital Management, LLC)
• Original Assignee: TQ Delta LLC (Techquity Capital Management, LLC)
• Inventors: Tzannes, Marcos C., Lund, Michael
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/372,841
• Publication Number:
  US 20170090811A1
• Time in Patent Office: 439 Days
• Field of Search: 714748, 714776, 714774, 714784, 711147, 711157, 375222, 709215
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/1809 Selective-repeat protocols
• CPC Class Codes: H04L 1/1835 Buffer management
• CPC Class Codes: H04L 1/1874 Buffer management
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/72 Routing based on the source address
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers

Abstract

A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Claims

1. A device comprising:

a transceiver operable to be configured with a first impulse noise protection requirement, the transceiver comprising a transmitter portion operable to transmit a first message after the transceiver has been configured with the first impulse noise protection requirement, wherein the first message indicates a first maximum number of bytes associated with an interleaver function of a transmit latency path and a first maximum number of bytes associated with a deinterleaver function of a receive latency path;

the transceiver further operable to be configured with a second impulse noise protection requirement, different than the first impulse noise protection requirement; and

the transmitter portion further operable to transmit a second message after the transceiver has been configured with the second impulse noise protection requirement, wherein the second message indicates a second maximum number of bytes associated with the interleaver function of the transmit latency path and a second maximum number of bytes associated with the deinterleaver function of the receive latency path,

wherein the first maximum number of bytes associated with the interleaver function of the transmit latency path is different than the second maximum number of bytes associated with the interleaver function of the transmit latency path, and

wherein the first maximum number of bytes associated with the deinterleaver function of the receive latency path is different than the second maximum number of bytes associated with the deinterleaver function of the receive latency.

2. The device of claim 1, further comprising a memory operable to be shared between the interleaver function of the transmitter portion associated with the transmit latency path and the deinterleaver function of the receiver portion associated with the receive latency path, wherein the first maximum number of bytes associated with the interleaver function is used to determine how much memory is used by the interleaver function and wherein the first maximum number of bytes associated with the deinterleaver function is used to determine how much memory is used by the deinterleaver function,

wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions of the memory are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes of the memory can be used by the deinterleaver function at a second time, different than the first time.

3. The device of claim 2, wherein the second maximum number of bytes associated with the interleaver function of the transmit latency path is used to determine how much memory is used by the interleaver function, and wherein the second maximum number of bytes associated with the deinterleaver function of the receive latency path is used to determine how much memory used by the deinterleaver function.

4. A device comprising:

a transceiver operable to be configured with a first data rate requirement, the transceiver comprising a transmitter portion operable to transmit a first message after the transceiver has been configured with the first data rate requirement, wherein the first message indicates a first maximum number of bytes associated with an interleaver function of a transmit latency path and a first maximum number of bytes associated with a deinterleaver function of a receive latency path;

the transceiver further operable to be configured with a second data rate requirement, different than the first data rate requirement; and

the transmitter portion further operable to transmit a second message after the transceiver has been configured with the second data rate requirement, wherein the second message indicates a second maximum number of bytes associated with the interleaver function of the transmit latency path and a second maximum number of bytes associated with the deinterleaver function of the receive latency path,

wherein the first maximum number of bytes associated with the interleaver function of the transmit latency path is different than the second maximum number of bytes associated with the interleaver function of the transmit latency path, and

wherein the first maximum number of bytes associated with the deinterleaver function of the receive latency path is different than the second maximum number of bytes associated with the deinterleaver function of the receive latency.

5. The device of claim 4, further comprising a memory wherein the memory is operable to be shared between the interleaver function of the transmitter portion associated with the transmit latency path and the deinterleaver function of the receiver portion associated with the receive latency path, wherein the first maximum number of bytes associated with the interleaver function is used to determine how much memory is used by the interleaver function and wherein the first maximum number of bytes associated with the deinterleaver function is used to determine how much memory is used by the deinterleaver function, and

wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions of the memory are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes of the memory can be used by the deinterleaver function at a second time, different than the first time.

6. The device of claim 5, wherein the second maximum number of bytes associated with the interleaver function of the transmit latency path is used to determine how much memory is used by the interleaver function, and wherein the second maximum number of bytes associated with the deinterleaver function of the receive latency path is used to determine how much memory used by the deinterleaver function.

7. A device comprising:

a transceiver operable to be configured with a first latency requirement, the transceiver comprising a transmitter portion operable to transmit a first message after the transceiver has been configured with the first latency requirement, wherein the first message indicates a first maximum number of bytes associated with an interleaver function of a transmit latency path and a first maximum number of bytes associated with a deinterleaver function of a receive latency path;

the transceiver further operable to be configured with a second latency requirement, different than the first latency requirement; and

the transmitter portion further operable to transmit a second message after the transceiver has been configured with the second latency requirement, wherein the second message indicates a second maximum number of bytes associated with the interleaver function of the transmit latency path and a second maximum number of bytes associated with the deinterleaver function of the receive latency path,

wherein the first maximum number of bytes associated with the interleaver function of the transmit latency path is different than the second maximum number of bytes associated with the interleaver function of the transmit latency path, and

wherein the first maximum number of bytes associated with the deinterleaver function of the receive latency path is different than the second maximum number of bytes associated with the deinterleaver function of the receive latency.

8. The device of claim 7, further comprising a memory wherein the memory is operable to be shared between the interleaver function of the transmitter portion associated with the transmit latency path and the deinterleaver function of the receiver portion associated with the receive latency path, wherein the first maximum number of bytes associated with the interleaver function is used to determine how much memory is used by the interleaver function and wherein the first maximum number of bytes associated with the deinterleaver function is used to determine how much memory is used by the deinterleaver function,

wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions of the memory are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes of the memory can be used by the deinterleaver function at a second time, different than the first time.

9. The device of claim 8, wherein the second maximum number of bytes associated with the interleaver function of the transmit latency path is used to determine how much memory is used by the interleaver function, and wherein the second maximum number of bytes associated with the deinterleaver function of the receive latency path is used to determine how much memory used by the deinterleaver function.