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Coordinated start interpretive execution exit for a multithreaded processor

  • US 9,898,289 B2
  • Filed: 10/20/2014
  • Issued: 02/20/2018
  • Est. Priority Date: 10/20/2014
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a memory;

    a processor coupled to the memory and comprising a computer processor core; and

    a plurality of threads executed by the computer processor core of the processor,wherein the plurality of threads comprises a first thread and remaining threads,wherein the system is configured to;

    determine, by the processor, that a start interpretive execution exit condition exists;

    determine, by the processor, that the computer processor core is within a grace period;

    enter, by the first thread, a start interpretive execution exit sync loop without signaling to any of the remaining threads;

    remain, by the first thread, in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop,determine, by the processor, that the grace period has expired for the computer processor core; and

    signal, by the first thread, each of the remaining threads to proceed to the corresponding start interpretive execution exit sync loop based on expiration of the grace period.

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