Coordinated start interpretive execution exit for a multithreaded processor

• US 9,898,289 B2
• Filed: 10/20/2014
• Issued: 02/20/2018
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Busaba, Fadi Y., Farrell, Mark S., Gainey, Jr., Charles W., Greiner, Dan F., Heller, Lisa C., Kubala, Jeffrey P., Osisek, Damian L., Schmidt, Donald W., Slegel, Timothy J.
• Primary Examiner(s): Mehta, Jyoti
• Application Number:
  US14/518,095
• Publication Number:
  US 20160110195A1
• Time in Patent Office: 1,219 Days
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Claims

1. A system comprising:

a memory;

a processor coupled to the memory and comprising a computer processor core; and

a plurality of threads executed by the computer processor core of the processor,

wherein the plurality of threads comprises a first thread and remaining threads,

wherein the system is configured to;

determine, by the processor, that a start interpretive execution exit condition exists;

determine, by the processor, that the computer processor core is within a grace period;

enter, by the first thread, a start interpretive execution exit sync loop without signaling to any of the remaining threads;

remain, by the first thread, in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop,

determine, by the processor, that the grace period has expired for the computer processor core; and

signal, by the first thread, each of the remaining threads to proceed to the corresponding start interpretive execution exit sync loop based on expiration of the grace period.

2. The system of claim 1, wherein the processor is configured to:

determine that the first thread is pending for a warning track interruption;

propagate warning track interruption pending condition by the first thread to each of the remaining threads; and

cause, by the first thread, the computer processor core to enter the grace period.

3. The system of claim 1, wherein the processor is configured to:

determine that a wait state is pending for the first thread;

determine that a warning track interruption pending condition exists for the first thread; and

enter the start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists.

4. The system of claim 3, wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the remaining threads.

5. The system of claim 1, wherein the first thread is a primary thread of the plurality of threads.

6. A computer program product, the computer program product comprising a computer readable storage medium having embodied therewith program instructions for executing a plurality of threads, including a first thread and remaining threads, on a computer processor core of a processor, the program instructions executable by the processor to cause the processor to:

determine that a start interpretive execution exit condition exists;

determine that the computer processor core is within a grace period;

enter, by the first thread, a start interpretive execution exit sync loop without signaling to any of the remaining threads;

remain by the first thread in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop,

determine that the grace period has expired for the computer processor core; and

signal, by the first thread, each of the remaining threads to proceed to the corresponding start interpretive execution exit sync loop based on expiration of the grace period.

7. The computer program product of claim 6, the program instructions executable by the processor to cause the processor to:

determine that the first thread is pending for a warning track interruption;

propagate warning track interruption pending condition by the first thread to each of the remaining threads; and

cause, by the first thread, the computer processor core to enter the grace period.

8. The computer program product of claim 6, the program instructions executable by the processor to cause the processor to:

determine that a wait state is pending for the first thread;

determine that a warning track interruption pending condition exists for the first thread; and

enter the start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists.

9. The computer program product of claim 8, wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the remaining threads.

10. The computer program product of claim 6, wherein the first thread is a primary thread of the plurality of threads.